DisplayPort Intel® Arria 10 FPGA IP Design Example User Guide

ID 683050
Date 12/13/2021
Public
Document Table of Contents

1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide

Updated for:
Intel® Quartus® Prime Design Suite 21.4
IP Version 20.0.0
The DisplayPort Intel® FPGA IP design examples for Intel® Arria® 10 devices feature a simulating testbench and a hardware design that supports compilation and hardware testing.

The DisplayPort Intel® FPGA IP offers the following design examples:

  • DisplayPort SST TX-only
  • DisplayPort SST RX-only
  • DisplayPort SST parallel loopback with a Pixel Clock Recovery (PCR) module
  • DisplayPort SST parallel loopback without a PCR module
  • DisplayPort MST parallel loopback with a PCR module
  • DisplayPort MST parallel loopback without a PCR module
  • High-bandwidth Digital Content Protection (HDCP) over DisplayPort
    Note: The HDCP feature is not included in the Intel® Quartus® Prime Pro Edition software. To access the HDCP feature, contact Intel at https://www.intel.com/content/www/us/en/broadcast/products/programmable/applications/connectivity-solutions.html.
When you generate a design example, the parameter editor automatically creates the files necessary to simulate, compile, and test the design in hardware.
Figure 1. Development Steps

Did you find the information on this page useful?

Characters remaining:

Feedback Message