DisplayPort Intel® Arria 10 FPGA IP Design Example User Guide

ID 683050
Date 2/01/2023
Public
Document Table of Contents

3.5.1. Security Considerations

When using the HDCP feature, be mindful of the following security considerations.
  • When designing a repeater system, you must block the received video from entering the TX IP in the following conditions:
    • If the received video is HDCP-encrypted (i.e. encryption status rx_hdcp1_enabled or rx_hdcp2_enabled from the RX IP is asserted) and the transmitted video is not HDCP-encrypted (i.e. encryption status tx_hdcp1_enabled or tx_hdcp2_enabled from the TX IP is not asserted).
    • If the received video is HDCP TYPE 1 (i.e. rx_streamid_type from the RX IP is asserted) and the transmitted video is HDCP 1.3 encrypted (i.e. encryption status tx_hdcp1_enabled from the TX IP is asserted)
  • You should maintain the confidentiality and integrity of your HDCP production keys, and any user encryption keys.
  • Intel strongly recommends you to develop any Intel® Quartus® Prime projects and design source files that contain encryption keys in a secure compute environment to protect the keys.
  • Intel strongly recommends you to use the design security features in FPGAs to protect the design, including any embedded encryption keys, from unauthorized copying, reverse engineering, and tampering.