DisplayPort Intel® Arria 10 FPGA IP Design Example User Guide

ID 683050
Date 2/01/2023
Public
Document Table of Contents

1.3. Generating the Design

Use the DisplayPort Intel® FPGA IP parameter editor in the Intel® Quartus® Prime software to generate the design example.
Figure 3. Generating the Design Flow
  1. Click Tools > IP Catalog, and select Intel® Arria® 10 as the target device family.
    Note: The design example only support Intel® Arria® 10 devices.
  2. In the IP Catalog, locate and double-click DisplayPort Intel® FPGA IP . The New IP Variation window appears.
  3. Specify a top-level name for your custom IP variation. The parameter editor saves the IP variation settings in a file named or <your_ip>.qsys .
  4. Select an Intel® Arria® 10 device in the Device field, or keep the default Intel® Quartus® Prime software device selection.
  5. Click OK. The parameter editor appears.
  6. Configure the desired parameters for both TX and RX.
    Note: The Nios II software has the capability to read and print out the DisplayPort Main Stream Attribute (MSA) information in the Nios II terminal. To read or print the MSA information, turn on the Enable GPU Control parameter.
  7. On the Design Example tab, select DisplayPort SST TX-only, DisplayPort SST RX-only, DisplayPort SST Parallel Loopback With PCR, DisplayPort SST Parallel Loopback Without PCR, DisplayPort MST Parallel Loopback With PCR, or DisplayPort MST Parallel Loopback Without PCR.
  8. Select Simulation to generate the testbench, and select Synthesis to generate the hardware design example.
    Note: DisplayPort MST design examples are supported only in synthesis; they are not supported in simulation.
    You must select at least one of these options to generate the design example files. If you select both, the generation time is longer.
  9. For Target Development Kit, select Arria 10 GX FPGA Development Kit . If you select the development kit, then the target device (selected in step 4) changes to match the device on the development kit. For Arria 10 GX FPGA Development Kit, the default device is 10AX115S2F45I1SG .
  10. Click Generate Example Design to generate the project files and the software Executable and Linking Format (ELF) programming file.

Did you find the information on this page useful?

Characters remaining:

Feedback Message