Ethernet Design Example Components User Guide

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ID 683044
Date 11/21/2023
Public

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Document Table of Contents
Document Table of Contents x
1. Time-of-day Clock 2. Time-of-day Synchronizer 3. Packet Classifier 4. Ethernet Design Example Components User Guide Archives 5. Document Revision History for the Ethernet Design Example Components User Guide
1. Time-of-day Clock x
1.1. Release Information 1.2. Resource Utilization 1.3. Configuring the TOD Clock 1.4. Using the TOD Clock 1.5. Interface Signals 1.6. Configuration Registers
1.1. Release Information x
1.1.1. Pulse Per Second Device Speed Grade Support
1.4. Using the TOD Clock x
1.4.1. Adjusting TOD Drift 1.4.2. Adjusting Offset, Jitter, and Wander 1.4.3. Correcting TOD Offset 1.4.4. IOPLL and TOD Setup for Pulse Per Second (Advanced Accuracy Mode)
1.4.4. IOPLL and TOD Setup for Pulse Per Second (Advanced Accuracy Mode) x
1.4.4.1. IOPLL and TOD Setup using Dynamic Phase Shift Interface 1.4.4.2. IOPLL and TOD Setup using IOPLL Reconfig IP
1.5. Interface Signals x
1.5.1. Avalon Memory-Mapped Signals 1.5.2. Time-of-day Signals 1.5.3. Pulse-Per-Second Signals 1.5.4. Clocking Requirements
2. Time-of-day Synchronizer x
2.1. Release Information 2.2. Resource Utilization 2.3. Configuring the TOD Synchronizer 2.4. Using the TOD Synchronizer 2.5. Interface Signals
2.4. Using the TOD Synchronizer x
2.4.1. Sampling Clock Frequency
3. Packet Classifier x
3.1. Release Information 3.2. Resource Utilization 3.3. Configuring the Packet Classifier 3.4. Interface Signals
3.4. Interface Signals x
3.4.1. Clock and Reset Signals 3.4.2. Avalon® Streaming Interface Signals 3.4.3. Control Signals
1. Time-of-day Clock
2. Time-of-day Synchronizer
3. Packet Classifier
4. Ethernet Design Example Components User Guide Archives
5. Document Revision History for the Ethernet Design Example Components User Guide

1.2. Resource Utilization

Table 3.  Estimated Resource Utilization in Stratix® V Devices (5SGXEA7H3F35C3)
Configuration ALMs Combinational ALUTs Logic Registers Memory

(M20K Blocks)

PERIOD_CLOCK_FREQUENCY = 0

OFFSET_JITTER_WANDER_EN = 0

 522 727 1038 0

PERIOD_CLOCK_FREQUENCY = 0

OFFSET_JITTER_WANDER_EN = 1

 1722 2729 2586 0

PERIOD_CLOCK_FREQUENCY = 1

OFFSET_JITTER_WANDER_EN = 0

 561 731 1230 0
Table 4.  Estimated Resource Utilization in Intel® Arria® 10 Devices (10AX115H1F34I1SG)
Configuration ALMs Combinational ALUTs Logic Registers Memory

(M20K Blocks)

PERIOD_CLOCK_FREQUENCY = 0

OFFSET_JITTER_WANDER_EN = 0

 512 752 1059 0

PERIOD_CLOCK_FREQUENCY = 0

OFFSET_JITTER_WANDER_EN = 1

 1618 2569 2648 0

PERIOD_CLOCK_FREQUENCY = 1

OFFSET_JITTER_WANDER_EN = 0

 581 814 1251 0
Table 5.  Estimated Resource Utilization in Intel® Stratix® 10 Devices (1SG280HN2F43E1VG )
Configuration ALMs Combinational ALUTs Logic Registers Memory

(M20K Blocks)

PERIOD_CLOCK_FREQUENCY = 0

OFFSET_JITTER_WANDER_EN = 0

ENABLE PPS = 0

 626 861 1309 0

PERIOD_CLOCK_FREQUENCY = 0

OFFSET_JITTER_WANDER_EN = 1

ENABLE PPS = 0

 1756 2698 2589 0

PERIOD_CLOCK_FREQUENCY = 1

OFFSET_JITTER_WANDER_EN = 0

ENABLE PPS = 0

 908 919 2560 0

PERIOD_CLOCK_FREQUENCY = 0

OFFSET_JITTER_WANDER_EN = 0

ENABLE_PPS = 1

PPS_ADVANCE = 0

 621 863 1311 0

PERIOD_CLOCK_FREQUENCY = 0

OFFSET_JITTER_WANDER_EN = 0

ENABLE_PPS = 1

PPS_ADVANCE = 1

 1086 1706 2020 1
Table 6.  Estimated Resource Utilization in Intel Agilex® 7 Devices (AGFB014R24A2E2V)
Configuration ALMs Combinational ALUTs Logic Registers Memory

(M20K Blocks)

PERIOD_CLOCK_FREQUENCY = 0

OFFSET_JITTER_WANDER_EN = 0

ENABLE PPS = 0

 575 812 1040 0

PERIOD_CLOCK_FREQUENCY = 0

OFFSET_JITTER_WANDER_EN = 1

ENABLE PPS = 0

 1706 2702 2589 0

PERIOD_CLOCK_FREQUENCY = 1

OFFSET_JITTER_WANDER_EN = 0

ENABLE PPS = 0

 706 868 1270 0

PERIOD_CLOCK_FREQUENCY = 0

OFFSET_JITTER_WANDER_EN = 0

ENABLE_PPS = 1

PPS_ADVANCE = 0

 576 814 1081 0

PERIOD_CLOCK_FREQUENCY = 0

OFFSET_JITTER_WANDER_EN = 0

ENABLE_PPS = 1

PPS_ADVANCE = 1

 1018 1660 1817 1
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