Ethernet Design Example Components User Guide

ID 683044
Date 11/21/2023

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Document Table of Contents

1.5.1. Avalon Memory-Mapped Signals

Table 10.   Avalon Memory-Mapped Signals Description
Name Direction Width Description
csr_address[] In n Use this bus to specify the register address you want to read from or write to.

By default, the width of this signal is 4. When the OFFSET_JITTER_WANDER_EN parameter is set to 1, the width of this signal is 5.

csr_read In 1 Assert this signal to request a read.
csr_readdata[] Out 32 Data read from the specified register.
csr_write In 1 Assert this signal to request a write.
csr_writedata[] In 32 Data to be written to the specified register.
clk In 1 Clock for the Avalon® memory-mapped interface, whose frequency is not more than 100 MHz.
rst_n In 1 Active-low reset signal for the clk domain. Synchronous to clk.