Ethernet Design Example Components User Guide

ID 683044
Date 11/21/2023
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2.3. Configuring the TOD Synchronizer

In the Intel® Quartus® Prime software, instantiate the TOD Synchronizer by selecting Ethernet IEEE 1588 TOD Synchronizer Intel® FPGA IP from the IP Catalog or Platform Designer (Interface Protocols > Ethernet > Reference Design Components). Specify the following parameters.

Table 18.  TOD Synchronizer Parameters Description
Name Valid Values Description
TOD_MODE 0, 1 Specifies the format of the time of day.
  • 0: 64 bits. 48 bits nanosecond and 16 bits fractional nanosecond.
  • 1: 96 bits. 48 bits seconds, 32 bits nanosecond and 16 bits fractional nanosecond.
The default value is 1.
SYNC_MODE 0 – 18 Specifies the synchronization type between the master and slave TOD clocks.
  • 0: 125-MHz master TOD clock and 156.25 MHz slave TOD clock.
  • 1: 156.25-MHz master TOD clock and 125-MHz slave TOD clock.
  • 2: The frequencies of the master and slave TOD clocks are the same, between 125 MHz and 402.83 MHz. This synchronization type supports different phase or PPM. Ensure that you also specify the period of the master and slave clocks using the PERIOD_NSEC and PERIOD_FNSEC parameters.
  • 3: 156.25-MHz master TOD clock and 312.5-MHz slave TOD clock.
  • 4: 312.5-MHz master TOD clock and 156.25-MHz slave TOD clock.
  • 5: 125-MHz master TOD clock and 312.5-MHz slave TOD clock.
  • 6: 312.5-MHz master TOD clock and 125-MHz slave TOD clock.
  • 7: 125-MHz master TOD clock and 390.625-MHz slave TOD clock.
  • 8: 390.625-MHz master TOD clock and 125-MHz slave TOD clock.
  • 9: 156.25-MHz master TOD clock and 390.625-MHz slave TOD clock.
  • 10: 390.625-MHz master TOD clock and 156.25-MHz slave TOD clock.
  • 11: 312.5-MHz master TOD clock and 390.625-MHz slave TOD clock.
  • 12: 390.625-MHz master TOD clock and 312.5-MHz slave TOD clock.
  • 13: 125-MHz master TOD clock and 62.5-MHz slave TOD clock.
  • 14: 156.25-MHz master TOD clock and 62.5-MHz slave TOD clock.
  • 15: 312.5-MHz master TOD clock and 62.5-MHz slave TOD clock.
  • 16: Reserved.
  • 17: Reserved.
  • 18: 125-MHz master TOD clock and 402.83-MHz slave TOD clock.

The default value is 1.

PERIOD_NSEC 0 – 4'hF Specifies the respective 4-bit nanosecond field for the reset value for the following clock frequencies:
  • 125 MHz: Set this parameter to 4'h8 for 8 ns.
  • 156.25 MHz: Set this parameter to 4'h6 for 6.4 ns. This value is the default value.
  • 312.5 MHz: Set this parameter to 4'h3 for 3.2 ns.
  • 390.625 MHz: Set this parameter to 4'h2 for 2.56 ns.
  • 402.83 MHz: Set this parameter to 4’h2 for 2.482 ns.

This parameter is only applicable for SYNC_MODE = 2.

PERIOD_FNSEC 0 – 16h'FFFF Specifies the respective 16-bit fractional nanosecond field for the reset value for the following clock frequencies:
  • 125 MHz: Set this parameter to 16'h0 for 8 ns.
  • 156.25 MHz: Set this parameter to 16'h6666 for 6.4 ns. This value is the default value.
  • 312.5 MHz: Set this parameter to 16'h3333 for 3.2 ns.
  • 390.625 MHz: Set this parameter to 16'h8F5C for 2.56 ns.
  • 402.83 MHz: Set this parameter to 16’h7B80 for 2.482 ns.

This parameter is only applicable for SYNC_MODE = 2.

SAMPLE_SIZE 64, 128, or 256 Specifies the number of samples to use in calculating the FIFO buffer’s fill level. More samples results in a more accurate estimation of the fill level. However, the calculation time increases with the number of samples.

The default value is 64.

This parameter is not applicable for SYNC_MODE = 18.