Ethernet Design Example Components User Guide

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ID 683044
Date 11/21/2023
Public

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Document Table of Contents
Document Table of Contents x
1. Time-of-day Clock 2. Time-of-day Synchronizer 3. Packet Classifier 4. Ethernet Design Example Components User Guide Archives 5. Document Revision History for the Ethernet Design Example Components User Guide
1. Time-of-day Clock x
1.1. Release Information 1.2. Resource Utilization 1.3. Configuring the TOD Clock 1.4. Using the TOD Clock 1.5. Interface Signals 1.6. Configuration Registers
1.1. Release Information x
1.1.1. Pulse Per Second Device Speed Grade Support
1.4. Using the TOD Clock x
1.4.1. Adjusting TOD Drift 1.4.2. Adjusting Offset, Jitter, and Wander 1.4.3. Correcting TOD Offset 1.4.4. IOPLL and TOD Setup for Pulse Per Second (Advanced Accuracy Mode)
1.4.4. IOPLL and TOD Setup for Pulse Per Second (Advanced Accuracy Mode) x
1.4.4.1. IOPLL and TOD Setup using Dynamic Phase Shift Interface 1.4.4.2. IOPLL and TOD Setup using IOPLL Reconfig IP
1.5. Interface Signals x
1.5.1. Avalon Memory-Mapped Signals 1.5.2. Time-of-day Signals 1.5.3. Pulse-Per-Second Signals 1.5.4. Clocking Requirements
2. Time-of-day Synchronizer x
2.1. Release Information 2.2. Resource Utilization 2.3. Configuring the TOD Synchronizer 2.4. Using the TOD Synchronizer 2.5. Interface Signals
2.4. Using the TOD Synchronizer x
2.4.1. Sampling Clock Frequency
3. Packet Classifier x
3.1. Release Information 3.2. Resource Utilization 3.3. Configuring the Packet Classifier 3.4. Interface Signals
3.4. Interface Signals x
3.4.1. Clock and Reset Signals 3.4.2. Avalon® Streaming Interface Signals 3.4.3. Control Signals
1. Time-of-day Clock
2. Time-of-day Synchronizer
3. Packet Classifier
4. Ethernet Design Example Components User Guide Archives
5. Document Revision History for the Ethernet Design Example Components User Guide

1.5.4. Clocking Requirements

  • Expect the clk frequency to be equal or less than 100 MHz.
  • The period_clk must have the same clock source as the timestamping consumer, e.g. MAC. In case the frequency exceeds 156.25 MHz, when OFFSET_JITTER_WANDER_EN is enabled, use the ToD in conjunction with the TOD Synchronizer.
  • For advanced accuracy Pulse per Second feature, IOPLL instantiation is required and must meet the following clocking requirements:
    • The IOPLL reference clock must be driven by TOD period clock or any clock with zero ppm difference from TOD period clock.
    • The IOPLL scan clock must be the same clock connecting to iopll_scan_clk. Set the iopll_scan_clk with any value between 50MHz and 100 MHz. The lower the frequency of the iopll_scan_clk, the longer the IOPLL takes to carry out the phase shift operation.
    • Set the pps_sampling_clk frequency as close as possible to the formula given in the interface description per Pulse-Per-Second Signals. Deviation from the formula can affect the accuracy of the PPS signal. However, a few MHz difference is acceptable and still gives an accuracy within 2ns range.
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