P-tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

ID 683038
Date 12/19/2022

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2.4. Compiling the Design Example

  1. Navigate to <project_dir>/intel_pcie_ptile_ast_0_example_design/ and open pcie_ed.qpf.
  2. If you select either of the two following development kits, the VID-related settings are included in the .qsf file of the generated design example, and you are not required to add them manually. Note that these settings are board-specific.
    • Intel® Stratix® 10 DX P-Tile Production FPGA development kit
    • Intel® Agilex™ F-Series P-Tile ES0 FPGA development kit
  3. On the Processing menu, select Start Compilation.