2.3. Simulating the Design Example
The simulation setup involves the use of a Root Port Bus Functional Model (BFM) to exercise the P-tile Avalon® Streaming IP for PCIe (DUT) as shown in the following figure.
Figure 15. PIO Design Example Simulation Testbench
For more details on the testbench and the modules in it, refer to Testbench.
The following flow diagram shows the steps to simulate the design example:
Figure 16. Procedure
- Change to the testbench simulation directory, <project_directory>/pcie_ed_tb/pcie_ed_tb/sim/<EDA_vendor>/simulator.
- Run the simulation script for the simulator of your choice. Refer to the table below.
- Analyze the results.
Note: P-Tile does not support parallel PIPE simulations.
|Siemens EDA QuestaSim*, Questa Intel® FPGA Edition
Note: From the Intel® Quartus® Prime 22.3 release onward, use the QuestaSim* 2022.3 version.
To run a simulation in interactive mode, use the following steps: (if you already generated a simv executable in non-interactive mode, delete the simv and simv.diadir)
The simulation reports, "Simulation stopped due to successful completion" if no errors occur.
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