P-tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

ID 683038
Date 12/19/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Give Feedback

2.6. Running the Design Example

Here are the test operations you can perform on the P-Tile Avalon® Streaming IP for PCIe design examples:
Table 3.  Test Operations Supported by the P-Tile Avalon® Streaming PCIe Design Examples
Operations Required BAR Supported by P-Tile Avalon® Streaming IP for PCIe Design Examples
PIO SR-IOV Performance
0: Link test - 100 writes and reads 0 Yes Yes No
1: Write memory space 0 Yes Yes No
2: Read memory space 0 Yes Yes No
3: Write configuration space N/A No No No
4: Read configuration space N/A No No No
5: Change BAR N/A Yes Yes No
6: Change device N/A Yes Yes No
7: Enable SR-IOV N/A No Yes No
8: Do a link test for every enabled virtual function belonging to the current device N/A No Yes No
9: Perform DMA for Throughput N/A No No Yes
For link stability when running the design examples on the Intel® Stratix® 10 DX FPGA Development Kit or the Intel® Agilex™ F-Series FPGA Development Kit, set the PCIe refclk switch to select the common refclk from the PCIe Edge Connector.
  • For the Intel® Stratix® 10 DX FPGA Development Kit, set SW14 to the OFF position to select the common refclk with the PCIe Host.
  • For the Intel® Agilex™ F-Series FPGA Development Kit, set SW7.1 to the OFF position to select the common refclk with the PCIe Host.