- Added a Note to the Simulating the Design Example section stating that QuestaSim 2022.3 is required to run simulations from Intel® Quartus® Prime 22.3 onward.
- Updated the simulation command for VCS in the Simulating the Design Example section.
- Updated the instructions in the Running the Performance Design Example section to include the step for choosing the payload size for DMA operations.
- Updated the Running the SR-IOV Design Example section to include sample enumeration results of running an SR-IOV design example with multiple PFs and VFs.
- Added support for Gen3 x8 and Gen4 x8 modes to the PIO design example.
- Removed support for the Intel® Stratix® 10 DX ES1 FPGA Development Kit from the Generating the Design Example section.
- Added the section Overview to describe the simulation and hardware testing support for all the design examples.
- Added instructions on how to run the Riviera* simulator to the Simulating the Design Example section.
- Added the section Running the Performance Design Example.
- Added a note to the Running the Design Example section stating that the refclk switch on the Intel® Stratix® 10 DX FPGA Development Kit or the Intel® Agilex™ FPGA Development Kit must be set to the OFF position to select the common refclk from the PCIe Edge Connector for PCIe link stability.
- Added the section Hardware and Software Requirements.
- Added the description for the Performance design example to the Design Example Description section.
- Added steps to generate the Performance design example to the Generating the Design Example section.
- Added the description for the Performance design example testbench to the Simulating the Design Example section.
- Changed the supported configurations for the SR-IOV design example from Gen3 x16 EP and Gen4 x16 EP to Gen3 x8 EP and Gen4 x8 EP in the Functional Description for the Single Root I/O Virtualization (SR-IOV) Design Example section.
- Added the support for the Intel® Stratix® 10 DX P-tile Production FPGA Development Kit to the Generating the Design Example section.
- Removed the simulation waveforms for the PIO and SR-IOV design examples from the section Simulating the Design Example.
- Updated the command to display the BDF in the section Running the PIO Design Example.
||Removed the Registers section since the Avalon Streaming design examples have no control register.
- Added simulation waveforms, test case descriptions and test result descriptions for the design examples.
- Added simulation instructions for the ModelSim simulator to the Simulating the Design Example section.
- Updated the document title to Intel FPGA P-Tile Avalon® streaming IP for PCI Express* Design Example User Guide to meet new legal naming guidelines.
- Updated the VCS interactive mode simulation command.
||Added SR-IOV design example description.
||Added Gen4 x8 Endpoint and Gen3 x8 Endpoint to the list of supported configurations.