P-tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

ID 683038
Date 9/26/2022
Public

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2.3. Simulating the Design Example

The simulation setup involves the use of a Root Port Bus Functional Model (BFM) to exercise the P-tile Avalon® Streaming IP for PCIe (DUT) as shown in the following figure.

Figure 15. PIO Design Example Simulation Testbench

For more details on the testbench and the modules in it, refer to Testbench.

The following flow diagram shows the steps to simulate the design example:

Figure 16. Procedure
  1. Change to the testbench simulation directory, <project_directory>/pcie_ed_tb/pcie_ed_tb/sim/<EDA_vendor>/simulator.
  2. Run the simulation script for the simulator of your choice. Refer to the table below.
  3. Analyze the results.
Note: P-Tile does not support parallel PIPE simulations.
Table 2.  Steps to Run Simulation
Simulator Working Directory Instructions
Siemens EDA QuestaSim*, Questa Intel® FPGA Edition <example_design>/pcie_ed_tb/pcie_ed_tb/sim/mentor/
  1. Invoke vsim (by typing vsim, which brings up a console window where you can run the following commands).
  2. do msim_setup.tcl
    Note: Alternatively, instead of doing Steps 1 and 2, you can type: vsim -c -do msim_setup.tcl.
  3. ld_debug
  4. run -all
  5. A successful simulation ends with the following message, "Simulation stopped due to successful completion!".
VCS* <example_design>/pcie_ed_tb/pcie_ed_tb/sim/synopsys/vcs
  1. Type sh vcs_setup.sh USER_DEFINED_COMPILE_OPTIONS="" USER_DEFINED_ELAB_OPTIONS="-xlrm\ uniq_prior_final" USER_DEFINED_SIM_OPTIONS=""
    Note: The command above is a single-line command.
  2. A successful simulation ends with the following message, "Simulation stopped due to successful completion!".
Note:
To run a simulation in interactive mode, use the following steps: (if you already generated a simv executable in non-interactive mode, delete the simv and simv.diadir)
  1. Open the vcs_setup.sh file and add a debug option to the VCS command: vcs -debug_access+r
  2. Compile the design example: sh vcs_setup.sh USER_DEFINED_ELAB_OPTIONS="-xlrm\ uniq_prior_final" SKIP_SIM=1
  3. Start the simulation in interactive mode: simv -gui &
Riviera* <example_design>/pcie_ed_tb/pcie_ed_tb/sim/aldec
  1. Invoke vsim by typing: vsim -c -do rivierapro_setup.tcl.
  2. ld_debug
  3. run -all
  4. A successful simulation ends with the following message, "Simulation stopped due to successful completion!".

The simulation reports, "Simulation stopped due to successful completion" if no errors occur.

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