P-tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

ID 683038
Date 9/26/2022
Public

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1.1. Overview

The following table presents an overview of the design examples supported by the P-tile Avalon® Streaming IP for PCI Express:
Table 1.  Design Examples Overview
Design Example Hard IP Mode Simulation Hardware
PIO Gen4 x16 512-bit Endpoint Supports Siemens EDA QuestaSim* , VCS* and Riviera-Pro* simulators. Supported for Intel® Stratix® 10 DX P-Tile Production FPGA Development Kit and Intel® Agilex™ F-Series P-Tile ES0/Production FPGA Development Kit.
Gen3 x16 512-bit Endpoint
Gen3 x16 256-bit Endpoint
Gen4 x8x8 512-bit (250 MHz or below) Endpoint
Gen4 x8x8 256-bit Endpoint
Gen3 x8x8 256-bit Endpoint
Gen4 x8 256-bit (350 MHz or above) Endpoint
Gen3 x8 256-bit Endpoint
SR-IOV Gen4 x16 512-bit (350 MHz or above) Endpoint Supports Siemens EDA QuestaSim*, VCS* and Riviera-Pro* simulators. Supported for Intel® Stratix® 10 DX P-Tile Production FPGA Development Kit and Intel® Agilex™ F-Series P-Tile ES0/Production FPGA Development Kit.
Gen3 x16 512-bit Endpoint
Gen4 x8x8 256-bit (350 MHz or above) Endpoint
Gen3 x8x8 256-bit Endpoint
Performance Gen4 x16 512-bit (500 MHz) Endpoint Supports VCS* simulator only. Supported for Intel® Stratix® 10 DX P-Tile Production FPGA Development Kit and Intel® Agilex™ F-Series P-Tile ES0/Production FPGA Development Kit. (*)
Note: (*) Supported in Intel® Quartus® Prime releases from 22.1 onward. For release 21.4, an Intel® Quartus® Prime patch is required. Refer to the Intel KDB for details.

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