Low Latency Ethernet 10G MAC Intel® Stratix® 10 FPGA IP Design Example User Guide

ID 683026
Date 4/10/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

7. Interface Signals Description

Use the following tables to find the description of the signals in the design example. The pinout diagram for each design example specifies the width of the signals.