Low Latency Ethernet 10G MAC Intel® Stratix® 10 FPGA IP Design Example User Guide

ID 683026
Date 4/10/2023
Public

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6.3. Functional Description

The design example consists of various components. The following block diagram shows the design components and the top-level signals of the design example.

Figure 34. Block Diagram—10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example Without IEEE 1588v2 Feature
Figure 35. Block Diagram—10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example With IEEE 1588v2 Feature