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1. Quick Start Guide
2. 10GBASE-R Ethernet Design Example
3. 10M/100M/1G/2.5G/10G Ethernet Design Example
4. 1G/2.5G Ethernet Design Example with IEEE 1588v2 Feature
5. 1G/2.5G/10G Ethernet Design Example with IEEE 1588v2 Feature
6. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example
7. Interface Signals Description
8. Configuration Registers Description
9. Low Latency Ethernet 10G MAC Intel® Stratix® 10 FPGA IP Design Example User Guide Archives
10. Document Revision History for the Low Latency Ethernet 10G MAC Intel® Stratix® 10 FPGA IP Design Example User Guide
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5.7. Configuration Registers
You can access the 32-bit configuration registers of the design components through the Avalon® memory-mapped interface.
Byte Offset | Block |
---|---|
0x00_0000 | Transceiver Reconfiguration |
0x00_4000 | TOD Master |
Channel 0 | |
0x01_0000 | MAC |
0x01_8000 | PHY |
0x01_A000 | Native PHY Reconfiguration |
Channel 1 | |
0x02_0000 | MAC |
0x02_8000 | PHY |
0x02_A000 | Native PHY Reconfiguration |
Traffic Controller | |
0x10_0000 | Traffic Controller |