F-Tile Ethernet Intel® FPGA Hard IP User Guide

ID 683023
Date 6/26/2023
Public

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2.2. Specifying the IP Core Parameters and Options

The F-Tile Ethernet Intel® FPGA Hard IP parameter editor allows you to quickly configure your custom IP variation. Use the following steps to specify IP core options and parameters in the Intel® Quartus® Prime Pro Edition software.
  1. If you do not already have an Intel® Quartus® Prime Pro Edition project in which to integrate your F-Tile Ethernet Intel® FPGA Hard IP, you must create one.
    1. In the Intel® Quartus® Prime Pro Edition, click File > New Project Wizard to create a new Quartus Prime project, or File > Open Project to open an existing Quartus Prime project. The wizard prompts you to specify a device.
    2. Specify the device family and select a production F-tile device.
    3. Click Finish.
  2. In the IP Catalog, locate and select F-Tile Ethernet Intel FPGA Hard IP. The New IP Variation window appears.
  3. Specify a top-level name for your new custom IP variation. The parameter editor saves the IP variation settings in a file named <your_ip> .ip.
  4. Click OK. The parameter editor appears.
  5. Specify the parameters for your IP core variation. Refer to F-Tile Ethernet Intel FPGA Hard IP Parameters for information about specific IP core parameters.
  6. Optionally, to generate a simulation testbench or hardware design example, follow the instructions in the F-Tile Ethernet Intel FPGA Hard IP Design Example User Guide.
  7. Click Generate HDL. The Generation dialog box appears.
  8. Select the IP-XACT setting to generate the .ipxact file containing register map information.
  9. Specify output file generation options, and then click Generate. The IP variation files generate according to your specifications.
  10. Click Close.
  11. After generating and instantiating your IP variation, make appropriate pin assignments to connect ports and set any appropriate per-instance RTL parameters.