F-Tile Ethernet Intel® FPGA Hard IP User Guide

ID 683023
Date 6/26/2023
Public

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7.13. 32-bit Soft CWBIN Counters

The F-Tile Ethernet Intel® FPGA Hard IP 32-bit Soft CWBIN Counters support all the FEC mode options available in the IP Parameter editor. This soft logic converts 8-bit CWBin0-3 registers in Ethernet Hard IP to 32-bit registers in soft logic. When the FEC codeword receives zero errors, the CWBin0 register counts up; When the FEC codeword receives 1 error, the CWBin1 register counts up, and so on.

Only the CWBin0-3 counters are expected to increase at a high rate. As a result, this Soft logic performs fast reads of these 8-bit counter values from Hard IP and accumulates these counts to 32-bit counter registers that you can access.

The F-Tile Ethernet Intel® FPGA Hard IP read rate is set to 6.5μs for 200/400G and 13μs for remaining rates to prevent the 8-bit counts from overflowing.