F-Tile Ethernet Intel® FPGA Hard IP User Guide

ID 683023
Date 6/26/2023
Public

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1.2.3. Resource Utilization

The resources for the F-Tile Ethernet Intel® FPGA Hard IP are obtained from the Intel® Quartus® Prime Pro Edition software version 21.3.
Table 7.  Resource Utilization for Intel Agilex® 7 DevicesThese results were obtained using the Intel® Quartus® Prime software version 21.3 with the following conditions:
  • PTP core variations is enabled with Timestamp accuracy mode set to Advanced.
  • The resource utilization excludes the soft logic utilization for the tile files, generated by Quartus after the Logic Generation phase.
    • The tiles files use approx. 5,000 combinatorial ALUTs, 6,000 logic registers, and 164,000 bits of block memory bits.
    • The PTP tile adapter uses approx. 216 combinatorial ALUTs, 174 logic registers, and 0 block memory bits.
Ethernet Rate IP Core Variation Combinatorial ALUTs Logic Registers Block Memory Bits
10G MAC Avalon® ST 848 1,282 2,240
MAC Avalon® ST with PTP 2,446 6,177 3,264
25G MAC Avalon® ST 850 1,288 2,240
MAC Avalon® ST with PTP 2,452 6,180 3,264
40G MAC Avalon® ST 2,136 4,045 0
50G MAC Avalon® ST 1,528 2,451 0
MAC Avalon® ST with PTP 3,320 7,992 1,024
100G MAC Avalon® ST 3,893 6,570 0
MAC Avalon® ST with PTP 7,964 17,578 1,024
200G MAC segmented 1,073 3,637 0
MAC segmented with PTP 4,531 16,119 1,024
400G MAC segmented 1,675 6,609 0
MAC segmented with PTP 11,033 34,269 2,048