F-Tile Ethernet Intel® FPGA Hard IP User Guide

ID 683023
Date 6/26/2023
Public

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12. Document Revision History for F-Tile Ethernet Intel® FPGA Hard IP User Guide

Document Version Intel® Quartus® Prime Version Changes
2023.06.26 23.2
  • Updated alignment marker verbiage in OTN Mode.
  • Added note in PTP RX Client Flow.
  • Added description about alignment marker for the signal name i_tx_pcs66_am inSignals of the PCS66 TX Interface table.
  • Updated ANLT functional description in Supported Modules and IPs.
  • Added note under AN channel in AN/LT parameters IP tab.
  • Added a verbiage about converting byte addressess to word addresses by shifting 2 bits to the right (divide by 4) in Registers.
  • Added a note verbiage "unauthorized access to register sets outside of the configured Ethernet fractures is not recommended" in Configuration Registers.
2023.04.03 23.1
  • Updated the following in the Round-trip latency table.
    • All the IEEE 802.3 RS(544,514) replaced with IEEE 802.3 RS(528,514) (CL91).
    • All the IEEE 802.3 RS(528,514) (CL91) replaced with IEEE 802.3 RS(544,514) (CL134).
  • Added steps to retrieve the N divider value in Clock Connections in Synchronous Ethernet Operation.
  • Removed the note "Enable TX packing feature is not available when PTP is turned on" in TX Packing Logic.
  • Updated ALMs numbers in TX Packing Logic section.
  • Updated Features in Precision Time Protocol section to include 200GE and 400GE modes for timestamp accuracy in advance mode.
  • Updated 200GE and 400GE Ethernet Data Rate to ± 1.5ns for advanced accuracy mode in PTP Timestamp Accuracy.
  • Added new topic: Routing Delay Adjustment for Basic Timestamp Accuracy Mode.
  • Updated the product family name to "Intel Agilex 7."
2022.12.19 22.4 Made the following changes:
  • Updated F-Tile Ethernet Intel FPGA Hard IP Block Diagram to remove filler text in F-Tile Ethernet Intel FPGA Hard IP Overview.
  • Added the following footnotes in Variant Selection table.
    • The Auto-negotiation and link training hardware is available for no FEC, IEEE 802.3 BASE-R Firecode (CL74), and IEEE 802.3 RS(528,514) (CL91).
    • The Auto-negotiation and link training is not available for IEEE 802.3 RS(544,514) (CL134).
  • Updated note about core speed grades for IP core variation with PTP in Device Speed Grade Support.
  • Added note about only 10GE with PTP support in advanced mode for OPNs AGIB041R29D1E2VR0, AGID041R29D1E2VR0, or any device density code of 041 in Device Speed Grade Support.
  • Added new topic: Round-trip Latency in F-Tile Ethernet Intel FPGA Hard IP Overview.
  • Updated Release Information.
  • Added the following parameters:
    • Include Deterministic Latency Measurement
    • Advanced Mode
    • Custom Ethernet line rate
  • Updated Include 32-bit soft CWBIN Counters default setting to Off in Parameters.
  • Updated Enable TX packing Parameter Description in Parameters.
  • Added i_sampling_clk in Clocks.
  • Added content for Example Design Generation of Synchronous Ethernet Operation in Clock Connections in Synchronous Ethernet Operation.
  • Updated the code for calculate pulse adjustment and FEC variants in PTP RX Client Flow.
  • Added a description for i_tx_pcs66_am in FlexE and OTN Mode TX Interface.
  • Added a description for o_rx_pcs66_am_valid in FlexE and OTN Mode RX Interface.
  • Added new subsection Deterministic Latency Measurement
  • Added auto-negotiation and link training feature note in Reset Signals.
  • Added reference to Pipelined Transfers of Avalon Interface Specifications in Reconfiguration Interfaces.
2022.09.26 22.3 Made the following changes:
  • Added Core Speed Grade/Transceiver Speed Grade table in Device Speed Grade Support.
  • Updated IP-XACT file information in Generating IP-XACT File.
  • Updated F-Tile Ethernet Intel FPGA Hard IP Block Diagram to include CWBIN in F-Tile Ethernet Intel FPGA Hard IP Overview.
  • Added 32-bit soft CWBIN counters parameter description in F-Tile Ethernet Intel FPGA Hard IP Overview.
  • Updated Release Information.
  • Added Include 32bit soft CWBIN counters and Reconfig clock frequency parameters in F-Tile Ethernet Intel FPGA Hard IP Parameters.
  • Added Enable IEEE 1588 PTP parameter description "When disabled, connect this port to 1'b0" in Clock Signals table.
  • Added new topic: 32-bit Soft CWBIN Counters.
  • Added note about auto-negotiation and link training bonding support for B0 FHT multi-lane designs in AN/LT Functional Description.
  • Added new topic: Implementation of Synchronous Ethernet (syncE) operation in Clocks section.
  • Corrected o_rx_mac_status_data's value 3'd3 to reserved in RX MAC Segmented Client Interface section.
2022.06.20 22.2 Made the following changes:
  • Updated note in Device Speed Grade Support.
  • Updated the PCS Mode RX Interface section to fix Hardware AM Cycle numbers.
  • Updated the Client Flow Glossary table in PTP Client Flow section. Added a row FL-Total number of FEC lanes of the variant.
  • Added new topic: Deterministic latency Interface.
  • Added new topic: TX Packing Logic.
  • Added Enable TX Packing and Include Deterministic Latency Interface parameters in F-Tile Ethernet Intel® FPGA Hard IP Parameters.
  • Fixed the broken link F-Tile Channel Placement Tool in Supported Tools.
2022.03.28 22.1 Made the following changes:
  • Updated the Variant Selection table. The Auto-negotiation and link training hardware is available for FHT NRZ 25GE-1, 50GE-2, and 100GE-4.
  • Added transceiver speed grade-related information in Device Speed Grade Support.
  • Added IP-XACT statement in Specifying the IP Core Parameters and Options.
  • Added new topic: Generating IP-XACT File
  • Updated caution note in Frame Padding to clarify 9-byte payload requirements.
  • Re-ordered step 7 and step 8 in PTP TX Client Flow.
  • Re-ordered step 9 and step 10 in PTP RX Client Flow.
  • Updated TX/RX hardware PMA delay for FHT transceivers in the UI Value and PMA Delay of Ethernet Modes table.
  • Updated the Clocks section to remove the PTP clock limitation. The PTP clock runs at 100 to 250 MHz.
  • Removed the CRC bytes statement in RX MAC Avalon ST Client Interface with Enabled Passthrough and RX CRC Forwarding.
  • Added reference to the .ipxact file generation in Configuration Registers.
  • Revised the i_rst_n reset description in the PTP Tile Adapter: Clocks, Reset, and Interface Ports section.
  • Removed Verilog file format specific note from the Auto-Negotiation and Link Training Parameters section. The IP supports VHDL for synthesis and simulation.
  • Updated F-Tile Ethernet Intel® FPGA Hard IP User Guide Archives.
2022.01.07 21.4 Made the following changes:
  • Updated F-Tile Ethernet Intel® FPGA Hard IP :
    • Added note about auto-negotiation and link training hardware support in Overview.
    • Added new section: Device Speed Grade Support.
    • Updated Generating Tile Files to include quartus_tlg updates.
    • Added the FHT precoding enable and Enable Native PHY Debug Endpoint parameters in the F-Tile Ethernet Intel® FPGA Hard IP Parameters.
    • Added PTP-specific i_reconfig_clk frequency range limitation.
  • Updated F-Tile Auto-Negotiation and Link Training for Ethernet Intel® FPGA IP :
    • Removed outdated 21.3 specific statement in Overview.
    • Updated Release Information.
    • Added note about VHDL limitation in F-Tile Auto-Negotiation and Link Training for Ethernet Intel® FPGA IP Parameters.
2021.10.04 21.3 Made the following changes:
  • Added support for PCS lane re-ordering in the Features table.
  • Removed 400GE-8 specific footnote from the Variant Selection table. 400GE-4 mode now supports auto-negotiation and link training.
  • Revised PTP description in F-Tile Ethernet Intel® FPGA Hard IP Overview,
  • Added Resource Utilization.
  • Updated F-Tile Ethernet Intel® FPGA Hard IP Parameters: IP Tab table:
    • Updated PMA reference frequency description.
    • Added PTP-related frequency requirements in the System PLL frequency description.
    • Added important note about hardware accuracy values in the Timestamp accuracy mode description.
    • Added new Enable Ethernet Debug Master Endpoint parameter
  • Added note in the TX MAC Segmented Client Interface.
  • Updated the TX TAM adjust calculation in PTP TX Client Flow.
  • Updated the RX TAM adjust calculation in PTP RX Client Flow.
  • Added new section: Routing Delay Adjustment for Advanced Timestamp Accuracy Mode
  • Updated Precision Time Protocol Interface:
    • Removed 40G Ethernet rate from the PTP Clocks table. 40G Ethernet rate does not support PTP feature
    • Corrected i_clk_tx_tod clock frequency from 250 MHz to 114.2857 MHz..
  • Revised step 6 in RX UI Adjustment.
  • Update simulation-based RX TAM values for 50G Ethernet rate in Reference Time (TAM) Interval.
  • Updated Hardware UX PMA delay values in the UI Value and PMA Delay of Ethernet Modes table.
  • Globally added a note about PTP timestamp accuracy. The note emphasizes that the specified timestamp accuracy values in base and advanced modes represent simulation-based results.
  • Updated Clock Signals descriptions for the following clock signals:
    • i_clk_tx
    • i_clk_rx
    • i_clk_pll
    • i_clk_ref
  • Revised text and updated figure in Clock Connections in PTP-Based Synchronous and Asynchronous Operation.
  • Corrected signal name from i_sl_tx_valid to i_tx_valid in the TX MAC Avalon ST Client Interface.
  • Revised fixed latency range in TX MAC Segmented Client Interface. The i_tx_mac_valid and o_tx_mac_ready signals can be spaced by a fixed latency between 1 to 8 clock cycles.
  • Revised i_clk_ptp_sample clock description in the PTP Clock Ports table.
  • Added new topic: Ethernet Toolkit Overview
2021.06.28 21.2 Initial release