F-Tile Ethernet Intel® FPGA Hard IP User Guide

ID 683023
Date 12/19/2022
Public

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7.4. TX MAC Segmented Client Interface

The F-Tile Ethernet Intel® FPGA Hard IP TX MAC segmented client interface allows you to write frame data to the TX MAC for transmission. The packets may start on any 8-byte segment.
Attention: To achieve the maximum throughput when using the TX MAC segmented interface, the input packets need to be packed tightly, leaving no idle segments in between.
Table 41.  Signals of the TX MAC Segmented Client InterfaceAll interface signals are clocked by the TX clock.

Signal Name

Width

Description

i_tx_mac_data[1023:0]

i_tx_mac_data[511:0]

i_tx_mac_data[255:0]

i_tx_mac_data[127:0]

i_tx_mac_data[63:0]

1024 bits (400GE)

512 bits (200GE)

256 bits (100GE)

128 bits (50GE/40GE)

64 bits (25GE/10GE)

Input data to the MAC when the rate is 10GE/25/40GE/50GE/100GE/200GE/400GE. Bit 0 is the LSB.
i_tx_mac_valid 1 bit

When asserted, the TX data signal is valid on this cycle. Must follow at a fixed latency relative to o_tx_mac_ready, and may go low during transmission of a packet.

When deasserted, values of input signals on the interface are hold constant.

i_tx_mac_inframe[15:0]

i_tx_mac_inframe[7:0]

i_tx_mac_inframe[3:0]

i_tx_mac_inframe[1:0]

i_tx_mac_inframe[0]

16 bits (400GE)

8 bits (200GE)

4 bits (100GE)

2 bits (50GE/40GE)

1 bits (25GE/10GE)

Indicates valid data in each segment for specific rate.

Along with the previous segment's inframe signal, this signal indicates the SOP and EOP location.

i_tx_mac_eop_empty[47:0]

i_tx_mac_eop_empty[23:0]

i_tx_mac_eop_empty[11:0]

i_tx_mac_eop_empty[5:0]

i_tx_mac_eop_empty[2:0]

48 bits (400GE)

24 bits (200GE)

12 bits (100GE)

6 bits (50GE/40GE)

3 bits (25GE/10GE)

The empty signal indicates the number of empty bytes in that segment at the end of the MAC frame.

o_tx_mac_ready

1 bit

The ready signal indicates the MAC is ready to receive data in normal operational mode.

i_tx_mac_error[15:0]

i_tx_mac_error[7:0]

i_tx_mac_error[3:0]

i_tx_mac_error[1:0]

i_tx_mac_error[0]

16 bits (400GE)

8 bits (200GE)

4 bits (100GE)

2 bits (50GE/40GE)

1 bits (25GE/10GE)

The error signal cause the TX frame treated as an error. Must assert in the segment where the frame ends.

i_tx_mac_skip_crc[15:0]

i_tx_mac_skip_crc[7:0]

i_tx_mac_skip_crc[3:0]

i_tx_mac_skip_crc[1:0]

i_tx_mac_skip_crc[0]

16 bits (400GE)

8 bits (200GE)

4 bits (100GE)

2 bits (50GE/40GE)

1 bits (25GE/10GE)

The skip CRC signal instructs the MAC to not insert CRC/PAD in a current packet. Must be asserted along with all valid data segments for the packet.

Figure 39. Transmitting Data Using the TX MAC Segmented Client Interface

The figure above shows how to transmit data using the TX MAC segmented client interface. In this example, the figure shows a 100GE port transmitting several packets, represented by 4 segments.

  • Packets may start on any 8-byte segment of i_tx_mac_data (Segmented). The i_tx_mac_inframe transition from 0 to 1 (between two consecutive segments) indicates a start of packet (SOP). The SOP begins at a segment where i_tx_mac_frame is set to 1.
  • For multisegmented interfaces, a new packet may start and the previous packet end are within the same cycle.
  • The byte order for the TX MAC segmented client interface is the reverse of the MAC Avalon ST client byte order. The bytes flow from right to left, LSB to MSB. The first transmitted byte from the interface is the i_tx_mac_data[7:0].
  • The bit order for the TX MAC segmented client interface is the same as the MAC Avalon ST client bit order. The first transmitted bit from the interface is the i_tx_mac_data[0].
    • The i_tx_mac_valid signal asserts only when the o_tx_mac_ready signal is asserted. The i_tx_mac_valid signal deasserts only when the o_tx_mac_ready signal is deasserted. Also, the i_tx_mac_valid may go low during the packet transmission.
    • The i_tx_mac_valid and the o_tx_mac_ready signals can be spaced by a fixed latency between 1 to 8 clock cycles.
    • When i_tx_mac_valid deasserts, i_tx_mac_data, i_tx_mac_inframe, i_tx_mac_eop_empty, i_tx_mac_error. and i_tx_skip_crc signals must be paused for as many cycles as o_tx_mac_ready is deasserted.
  • When the frame ends, i_tx_mac_eop_empty is set to the number of unused bytes in i_tx_mac_data.
    • The i_tx_mac_eop_empty transition from 1 to 0 (between two consecutive segments) indicates the end of packet (EOP). The EOP ends in the segment where i_tx_mac_inframe is set to 0.
    • The minimum number of bytes on the last cycle is 1.