F-Tile Ethernet Intel® FPGA Hard IP User Guide

ID 683023
Date 12/19/2022

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5.3. Clock Connections in MAC Asynchronous FIFO Operation

When you enable Enable asynchronous adapter clocks, i_clk_tx and i_clk_rx input clock signals can be asynchronous from each other and from o_clk_pll clock provided that the clocks are fast enough to ensure the IP core channel processes all data.
Figure 22. Clock Connections in MAC Asynchronous Client FIFO Operation
The table below summarizes minimum frequencies required for i_clk_tx and i_clk_rx during the Asynchronous mode.
Table 27.  Minimum Supported Clock Rates for MAC Client Asynchronous FIFO Operation
Ethernet Data Rate Clock Rate
Min i_clk_tx Min i_clk_rx
10G 156.25 MHz

o_clk_rec_div or

156.25 MHz + 100 PPM

25G/50G 390.625 MHz

o_clk_rec_div or

390.625 MHz + 100 PPM

40G 312.5 MHz 312.5 MHz + 100 PPM
100G with enabled Preamble Passthrough 380 MHz 380 MHz
100G with disabled Preamble Passthrough 340 MHz 340 MHz