F-Tile Ethernet Intel® FPGA Hard IP User Guide

ID 683023
Date 12/19/2022
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7.15.4. RX Timestamp Interface

The RX timestamp interface provides RX timestamps for any received packets.

Each RX packet contains a timestamp, recorded in the o_ptp_rx_its bus. The timestamp signals are valid when o_rx_valid and o_rx_startofpacket signals are high.

Figure 60. Using the IEEE 1588 RX Timestamp Interface The figure depicts two RX packet containing two RX packets and their respective ingress timestamps.
Table 64.  Signals of the RX Timestamp InterfaceAll interface signals are clocked by i_clk_rx clock. The timestamp is always in 1588 v2 format.

Signal Name

Width

Description

o_ptp_rx_its[95:0]

o_ptp_rx_its[191:0]

96 bits (10GE/25GE,50GE/100GE/200GE)

192 bits (400GE)

Ingress timestamp signal for the incoming RX packets when Ethernet rate is 10GE/25GE,50GE/100GE/200GE/400GE.
  • For RX MAC Avalon ST client interface, o_ptp_rx_its[95:0] is valid only when both, o_rx_valid and o_rx_startofpacket signals, are equal to 1.
  • For RX MAC segmented client interface, o_ptp_rx_its[95:0] is valid only when o_rx_valid is equal to 1 and o_rx_mac_inframe[7:0] contains the start of the packet (SOP).

    The o_ptp_rx_its[191:96] is valid only when o_rx_valid is equal to 1 and o_rx_mac_inframe[15:8] contains the SOP.