F-Tile Ethernet Intel® FPGA Hard IP User Guide

ID 683023
Date 12/19/2022
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7.7. PCS Mode TX Interface

The F-Tile Ethernet Intel® FPGA Hard IP TX client interface in PCS variations employs the Media Independent Interface (MII) protocol.

The client acts as a source and the TX PCS acts as a sink in the transmit direction.

Table 48.  Signals of the MII TX Client InterfaceAll interface signals are clocked by the TX clock. The signal names are standard Avalon® streaming interface signals.

Signal Name

Width

Description

i_tx_mii_d[1023:0]

i_tx_mii_d[511:0]

i_tx_mii_d[255:0]

i_tx_mii_d[127:0]

i_tx_mii_d[63:0]

1024 bits (400GE)

512 bits (200GE)

256 bits (100GE)

128 bits (40GE/50GE)

64 bits(10GE/25GE)

TX MII data. Data must be in MII encoding. i_tx_mii_d[7:0] holds the first byte the IP core transmits on the Ethernet link. i_tx_mii_d[0] holds the first bit the IP core transmits on the Ethernet link.

While the TX MII valid signal has the value of 0 or the alignment marker insertion bit signal has the value of 1, and for one additional clock cycle, you must hold the value of this signal stable, a behavior called freezing the signal value.

i_tx_mii_c[127:0]

i_tx_mii_c[63:0]

i_tx_mii_c[31:0]

i_tx_mii_c[15:0]

i_tx_mii_c[7:0]

128 bits (400GE)

64 bits (200GE)

32 bits (100GE)

16 bits (40GE/50GE)

8 bits(10GE/25GE)

TX MII control bits. Each bit corresponds to a byte of the TX MII data signal. For example, i_tx_mii_c[0] corresponds to i_tx_mii_d[7:0], i_tx_mii_c[1] corresponds to i_tx_mii_d[15:8], and so on.

If the value of a bit is 1, the corresponding data byte is a control byte. If the value of a bit is 0, the corresponding data byte is data.

i_tx_mii_valid

1 bit Indicates that the TX MII data signal is valid.

You must assert this signal a fixed number of clock cycles after the IP core raises ready signal, and must deassert this signal the same number of clock cycles after the IP core deasserts the ready signal. The number must be in the range of 1–6 clock cycles.

o_tx_mii_ready

1 bit Indicates the PCS is ready to receive new data.

i_tx_mii_am

1 bit Alignment marker insertion bit.
Figure 42. Transmitting Data Using the PCS Mode TX Interface

The figure above shows how to write packets directly to the PCS mode TX interface.

  • The packets are written using MII.
    • Each byte in i_tx_mii_d has a corresponding bit in i_tx_mii_c that indicates whether the byte is a control byte or a data byte; for example, i_tx_mii_c[1] is the control bit for i_tx_mii_d[15:8].
  • i_tx_mii_valid should conform to these conditions:
    • Assert the valid signal only when the ready signal is asserted, and deassert only when the ready signal is deasserted.
    • The two signals can be spaced by a fixed latency between 1 and 6 cycles.
    • When the valid signal deasserts, i_tx_mii_d and i_tx_mii_c must be paused.
  • The byte order for the PCS mode TX interface is opposite of the byte order for the MAC Avalon® streaming interface. Bytes flow from LSB to MSB; the first byte to be transmitted from the interface is i_tx_mii_d[7:0].
  • The bit order for the PCS mode TX interface is the same as the bit order of the MAC client. The first bit to be transmitted from the interface is i_tx_mii_d[0].
Note: The PCS mode TX interface is not SOP aligned. Any legal ordering of packets in MII format is accepted.
Table 49.  Writing a Start Packet Block with Preamble to the PCS Mode TX Interface
MII Data MII Control Ethernet Packet Byte
i_tx_mii_d[7:0] 0xFB i_tx_mii_c[0] 1 Start of Packet
i_tx_mii_d[15:8] 0x55 i_tx_mii_c[1] 0 Preamble
i_tx_mii_d[23:16] 0x55 i_tx_mii_c[2] 0 Preamble
i_tx_mii_d[31:24] 0x55 i_tx_mii_c[3] 0 Preamble
i_tx_mii_d[39:32] 0x55 i_tx_mii_c[4] 0 Preamble
i_tx_mii_d[47:40] 0x55 i_tx_mii_c[5] 0 Preamble
i_tx_mii_d[55:48] 0x55 i_tx_mii_c[6] 0 Preamble
i_tx_mii_d[63:56] 0xD5 i_tx_mii_c[7] 0 SFD
Figure 43. Inserting Alignment Markers

The fabric controls the timing of alignment marker insertion. Alignment markers cannot be delayed without disrupting the Ethernet link. Use valid cycles to count the alignment markers. When i_tx_mii_valid is low, the alignment marker counters and input must freeze.

For alignment marker counts, you only use valid cycles. When i_tx_mii_valid is low, the alignment marker counters and input data must freeze.

The number of cycles for i_tx_mii_am to remain high depends on the rate of the interface.

  • 400GE: 2 cycles
  • 200GE: 2 cycles
  • 100GE: 5 cycles
  • 50GE-2 with RS-FEC or 50GE-1for IEEE: 2 cycles
  • 50GE-2 without RS-FEC or 40GE: 2 cycles
  • 25GE with RS-FEC: 4 cycles)

The number of cycles for am period depends on the rate of the interface and whether in simulation or hardware.

  • In simulation, it is common to use a reduced am period for both sides of the link to increase lock-time speed.
    • 400GE: 640
    • 200GE: 640
    • 100GE: 1280
    • 50GE-2 with RS-FEC: 512
    • 50GE-2 without RS-FEC or 50GE: 640
    • 40GE: 128
    • 25GE with RS-FEC: 1280
  • In hardware.
    • 400GE: 40960
    • 200GE: 40960
    • 100GE: 81920
    • 50GE-2 with RS-FEC RS(272,258) or 50GE-1 for IEEE: 40960
    • 40GE or 50GE-2 without RS-FEC: 32768
    • 25GE with RS-FEC: 81920

For proper operation, program the MAC, PCS, and optional FEC to use the same am period.

In FEC modes, the TX datapath does not come completely out of reset until at least 2 alignment marker periods passed. You must start driving i_tx_mii_am at the proper interval before o_tx_pll_lanes_stable goes high. You may drive the signal as soon as o_tx_pll_locked has gone high and o_tx_mii_ready starts toggling. When the external custom rate interface is enabled, you must start driving i_custom_cadence. For more information, refer to the Custom Rate Interface.