F-Tile Ethernet Intel® FPGA Hard IP User Guide

ID 683023
Date 9/26/2022

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5.5. Clock Connections in Synchronous Ethernet Operation

When you enable the Synchronous Ethernet (SyncE) operation, two or more channels can share the off-chip cleanup PLL clock output.

The Synchronous Ethernet standard, described in the ITU-T G.8261, G.8262, and G.8264 recommendations, requires that the TX clock be filtered to maintain synchronization with the RX reference clock through a sequence of nodes. The expected usage is that user logic drives the transceiver reference clocks with a filtered version of the RX recovered clock signal, to ensure the receive and transmit functions remain synchronized. In this usage model, a design component outside the IP core performs the filtering off chip.

In the diagram below, the recovered clock outputs from the IPs can be connected to the off-chip cleanup PLL using tile PIN. In F-tile, the recovered clock from the FGT PMA can be driven to dedicated clock output pins on the tile itself. Each F-tile has only two such clock outputs: FGT QUADs 2 and 3. Each has one dedicated clock output pin (Refclk8/9).

The primary and backup cleanup clocks come from recovered clock output pins from a pair of ports connected to remote stations on the same SyncE network, with the transceiver reference clock is sourced from the output of the cleanup PLL.

In the diagram below, out_cdr_clk0 is the clock that goes to off-chip cleanup PLL.

Figure 24. Clock Connection of Sync-E clock through CDR clock out pin
Note: You must set the Custom Cadence mode to match the PPM difference between clocks when the Ethernet IP system clock is derived from a different reference clock than the transceiver clock.

Implementation of Synchronous Ethernet (SyncE) Operation

To enable the recovered clock output from F-tile, select the Enable dedicated CDR Clock Output in the IP parameter editor as shown below.
Figure 25. Enable dedicated CDR Clock Output IP Parameter Editor

The output frequency is equal to the nominal incoming refclk divided by any pre-divider on the RX path.

The table below shows the recovered clock frequencies with respect to input reference clock.
Table 27.  Recovered Clock Frequency
NRZ/PAM4 Input Refclk (MHz) N divider Output Recovered Clk (MHz)
NRZ 156.25 4 39.0625
312.5 8 39.0625
322.265625 12 39.0625
PAM4 156.25 6 26.0417
Note: Make sure the DUT top signal o_cdr_divclk is connected to the system PLL IP.
To connect to the system PLL, select Enable FGT CDR Output in the IP parameter editor, as shown in the figure below.
Figure 26. System PLL Clocks Intel FPGA IP
Note: In the IP Parameter Editor, you can Enable the dedicated CDR clock output for multiple IPs. However, if you want to enable two dedicated CDR clock outputs from different IPs, Enable FGT CDR Output #0 and Enable FGT CDR Output #1 must be enabled in the system PLL.