F-Tile Ethernet Intel® FPGA Hard IP User Guide

ID 683023
Date 9/26/2022
Public

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4.2.3.4. Pause Control Frame Filtering

The F-Tile Ethernet Intel® FPGA Hard IP supports options to enable or disable the following features for incoming pause control frames. These options are available if you do not set the Stop TX traffic when link partner sends pause parameter to Disable Flow Control.

For filtering, the PAUSE and PFC packets are only processed if their destination address matches the address given in the rx_pause_daddr register.

  • If you turn on Forward RX Pause Requests in the parameter editor, the RX PAUSE and PFC frames are always passed along the RX client, even if they are processed.
  • If you turn off Forward RX Pause Requests in the parameter editor, the RX PAUSE and PFC packets are processed internally, and not presented to the RX client as valid packets.

A PAUSE or PFC packet must have a destination address that matches the rx_pause_daddr register, a Length/Type field that is set to 0x8808, and the first 2 bytes of the packet set to 0x0001 or 0x0101.

To actually trigger PAUSE or PFC, you must also ensure that the packets are of the correct length and have no FCS error. Because these conditions are not known until the whole packet has arrived, if you turn off Forward RX Pause Requests, you may have packets that are filtered because they look like PAUSE or PFC packets, but not processed because they are of the wrong size or have an error.