F-Tile Ethernet Intel® FPGA Hard IP User Guide

ID 683023
Date 9/26/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Give Feedback

1.2.1. Device Family Support

Table 4.   Intel® FPGA IP Core Device Support Levels

Device Support Level

Definition

Advance

The IP core is available for simulation and compilation for this device family. Timing models include initial engineering estimates of delays based on early post-layout information. The timing models are subject to change as silicon testing improves the correlation between the actual silicon and the timing models. You can use this IP core for system architecture and resource utilization studies, simulation, pinout, system latency assessments, basic timing assessments (pipeline budgeting), and I/O transfer strategy (datapath width, burst depth, I/O standards tradeoffs).

Preliminary

The IP core is verified with preliminary timing models for this device family. The IP core meets all functional requirements, but might still be undergoing timing analysis for the device family. It can be used in production designs with caution.

Final

The IP core is verified with final timing models for this device family. The IP core meets all functional and timing requirements for the device family and can be used in production designs.

Table 5.   F-Tile Ethernet Intel® FPGA Hard IP Core Device Family SupportShows the level of support offered by the F-Tile Ethernet Intel® FPGA Hard IP for each Intel FPGA device family.

Device Family

Support

Intel® Agilex™

Advance

Other device families

No support