F-Tile Ethernet Intel® FPGA Hard IP User Guide

ID 683023
Date 9/26/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Give Feedback

7.6. MAC Flow Control Interface

The F-Tile Ethernet Intel® FPGA Hard IP MAC flow control interface in MAC Avalon ST or MAC segmented variation indicates and receives flow control events notifications.
Table 46.  MAC Flow Control InterfaceAll interface signals are clocked by the i_clk_tx clock. For 10GE/25GE channels, all interface signals are asynchronous.

Signal Name

Width

Description

i_tx_pause 1 bit

When asserted, directs the IP core to send a PAUSE XOFF frame on the Ethernet link.

Note: For 10GE/25GE channels, you should hold the i_tx_pause signal more than 205 ns to get the request captured by the MAC.
i_tx_pfc[7:0] 8 bits

When a bit is asserted, directs the IP core to send a PFC XOFF frame on the Ethernet link for the corresponding priority queue.

Note: For 10GE/25GE channels, you should hold the i_tx_pfc signal more than 205 ns to get the request captured by the MAC.

The rising edge triggers the request. You must maintain this signal at the value of 1 until you want the IP core to end the pause period. The IP core sends a PFC XOFF frame after it completes processing of the current in-flight TX packet, and periodically thereafter, until you deassert the i_tx_pfc bit. When you deassert the bit, the IP core sends a PFC XON frame on the Ethernet link for the corresponding priority queue. This signal is functional only if priority flow control is enabled.

o_rx_pause 1 bit

When asserted, indicates the IP core received a PAUSE XOFF frame on the Ethernet link.

o_rx_pfc[7:0] 8 bits

When a bit is asserted, indicates the IP core received a PFC XOFF frame on the Ethernet link for the corresponding priority queue.