F-Tile Ethernet Intel® FPGA Hard IP User Guide

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ID 683023
Date 3/28/2022
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Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. F-Tile Ethernet Intel® FPGA Hard IP Parameters 4. Functional Description 5. Clocks 6. Resets 7. Interface Overview 8. Configuration Registers 9. Supported Modules and IPs 10. Supported Tools 11. F-Tile Ethernet Intel® FPGA Hard IP User Guide Archives 12. Document Revision History
1. Overview x
1.1. Ethernet System in F-Tile Overview 1.2. F-Tile Ethernet Intel® FPGA Hard IP Overview
1.2. F-Tile Ethernet Intel® FPGA Hard IP Overview x
1.2.1. Device Family Support 1.2.2. Device Speed Grade Support 1.2.3. Resource Utilization 1.2.4. Release Information
2. Getting Started x
2.1. Installing and Licensing F-Tile Ethernet Intel® FPGA Hard IP Cores 2.2. Specifying the IP Core Parameters and Options 2.3. Reference and System PLL Clock for your IP Design 2.4. Generated File Structure 2.5. Generating Tile Files 2.6. IP Core Testbenches
2.4. Generated File Structure x
2.4.1. Generating IP-XACT File
4. Functional Description x
4.1. Datapath Description 4.2. F-Tile Ethernet Intel® FPGA Hard IP MAC 4.3. PCS, OTN, and FlexE Modes 4.4. Precision Time Protocol 4.5. Auto-Negotiation and Link Training
4.2. F-Tile Ethernet Intel® FPGA Hard IP MAC x
4.2.1. MAC TX Datapath 4.2.2. MAC RX Datapath 4.2.3. Congestion and Flow Control Using PAUSE or Priority Flow Control (PFC) 4.2.4. Link Fault Signaling 4.2.5. Order of Ethernet Transmission
4.2.1. MAC TX Datapath x
4.2.1.1. TX Preamble, Start, and SFD Insertion 4.2.1.2. Source Address Insertion 4.2.1.3. Length/Type Field Processing 4.2.1.4. Frame Padding 4.2.1.5. Frame Check Sequence (CRC-32) Insertion 4.2.1.6. Inter-Packet Gap Generation and Insertion
4.2.2. MAC RX Datapath x
4.2.2.1. RX Preamble Processing 4.2.2.2. RX Strict SFD Checking 4.2.2.3. RX FCS Checking 4.2.2.4. RX Malformed Packet Handling 4.2.2.5. Removing PAD Bytes and FCS Bytes from RX Frames 4.2.2.6. RX Undersized Frames, Oversized Frames, and Frames with Length Errors 4.2.2.7. Inter-Packet Gap
4.2.3. Congestion and Flow Control Using PAUSE or Priority Flow Control (PFC) x
4.2.3.1. Conditions Triggering XOFF Frame Transmission 4.2.3.2. Conditions Triggering XON Frame Transmission 4.2.3.3. Pause Control and Generation Interface 4.2.3.4. Pause Control Frame Filtering
4.3. PCS, OTN, and FlexE Modes x
4.3.1. PCS Mode 4.3.2. OTN Mode 4.3.3. FlexE Mode
4.4. Precision Time Protocol x
4.4.1. Features 4.4.2. PTP Timestamp Accuracy 4.4.3. PTP Client Flow 4.4.4. RX Virtual Lane Offset Calculation for No FEC Variants 4.4.5. Virtual Lane Order and Offset Values 4.4.6. UI Adjustment 4.4.7. Reference Time Interval 4.4.8. Minimum and Maximum Reference Time (TAM) Interval for UI Measurement (Hardware) 4.4.9. UI Value and PMA Delay 4.4.10. Routing Delay Adjustment for Advanced Timestamp Accuracy Mode
4.4.3. PTP Client Flow x
4.4.3.1. PTP TX Client Flow 4.4.3.2. PTP RX Client Flow
4.4.6. UI Adjustment x
4.4.6.1. TX UI Adjustment 4.4.6.2. RX UI Adjustment
5. Clocks x
5.1. Clock Connections in Single Instance Operation 5.2. Clock Connections in Multiple Instance Operation 5.3. Clock Connections in MAC Asynchronous FIFO Operation 5.4. Clock Connections in PTP-Based Synchronous and Asynchronous Operation 5.5. Clock Connections in Synchronous Ethernet Operation 5.6. Custom Cadence
6. Resets x
6.1. Reset Signals 6.2. Reset Sequence
7. Interface Overview x
7.1. Status Interface 7.2. TX MAC Avalon ST Client Interface 7.3. RX MAC Avalon ST Aligned Client Interface 7.4. TX MAC Segmented Client Interface 7.5. RX MAC Segmented Client Interface 7.6. MAC Flow Control Interface 7.7. PCS Mode TX Interface 7.8. PCS Mode RX Interface 7.9. FlexE and OTN Mode TX Interface 7.10. FlexE and OTN Mode RX Interface 7.11. Custom Rate Interface 7.12. Reconfiguration Interfaces 7.13. Precision Time Protocol Interface
7.2. TX MAC Avalon ST Client Interface x
7.2.1. TX MAC Avalon ST Client Interface with Disabled Preamble Passthrough 7.2.2. TX MAC Avalon ST Client Interface with Enabled Preamble Passthrough 7.2.3. Using MAC Avalon ST skip_crc Signal to Control Source Address, PAD, and CRC Insertion 7.2.4. Using MAC Avalon ST i_tx_error Signal to Mark Packets Invalid
7.3. RX MAC Avalon ST Aligned Client Interface x
7.3.1. RX MAC Avalon ST Client Interface with Disabled Preamble Passthrough 7.3.2. RX MAC Avalon ST Client Interface with Enabled Passthrough and RX CRC Forwarding 7.3.3. RX MAC Adapter Limitations 7.3.4. RX MAC Avalon ST Client Interface Status
7.4. TX MAC Segmented Client Interface x
7.4.1. TX MAC Segmented Client Interface with Disabled Preamble Passthrough 7.4.2. TX MAC Segmented Client Interface with Enabled Preamble Passthrough 7.4.3. Using MAC Segmented skip_crc Signal to Control Source Address, PAD, and CRC Insertion 7.4.4. Using MAC Segmented i_tx_mac_error to Mark Packets Invalid
7.5. RX MAC Segmented Client Interface x
7.5.1. RX MAC Segmented Client Interface with Disabled Preamble Passthrough 7.5.2. RX MAC Segmented Client Interface with Enabled Passthrough and RX CRC Forwarding 7.5.3. RX MAC Segmented Client Interface Status and Errors
7.12. Reconfiguration Interfaces x
7.12.1. Ethernet Reconfiguration Interfaces 7.12.2. Transceiver Reconfiguration Interfaces
7.13. Precision Time Protocol Interface x
7.13.1. Time-of-Day Interface 7.13.2. TX 2-Step Timestamp Interface 7.13.3. TX 1-Step Timestamp Interface 7.13.4. RX Timestamp Interface 7.13.5. PTP Status Interface 7.13.6. PTP Tile Interface
7.13.3. TX 1-Step Timestamp Interface x
7.13.3.1. PTP Field Offset for 1-Step Operation
8. Configuration Registers x
8.1. Ethernet Avalon® Memory-Mapped Interface Address Space 8.2. Transceiver Avalon® Memory-Mapped Interface Address Space
8.1. Ethernet Avalon® Memory-Mapped Interface Address Space x
8.1.1. Ethernet Hard IP Core CSRs 8.1.2. FEC and Transceiver Control and Status Registers
9. Supported Modules and IPs x
9.1. F-Tile Auto-Negotiation and Link Training For Ethernet Intel® FPGA IP 9.2. PTP Tile Adapter
9.1. F-Tile Auto-Negotiation and Link Training For Ethernet Intel® FPGA IP x
9.1.1. Overview 9.1.2. Release Information 9.1.3. Functional Description 9.1.4. Parameters 9.1.5. Clocks and Resets 9.1.6. Registers
9.2. PTP Tile Adapter x
9.2.1. Overview 9.2.2. Clocks, Reset, and Interface Ports 9.2.3. PTP Asymmetry Delay Reconfiguration Interface 9.2.4. PTP Peer-to-Peer MeanPathDelay Reconfiguration Interface
10. Supported Tools x
10.1. F-Tile Channel Placement Tool 10.2. Ethernet Toolkit Overview
10.2. Ethernet Toolkit Overview x
10.2.1. Features
1. Overview
2. Getting Started
3. F-Tile Ethernet Intel® FPGA Hard IP Parameters
4. Functional Description
5. Clocks
6. Resets
7. Interface Overview
8. Configuration Registers
9. Supported Modules and IPs
10. Supported Tools
11. F-Tile Ethernet Intel® FPGA Hard IP User Guide Archives
12. Document Revision History

7.5. RX MAC Segmented Client Interface

The F-Tile Ethernet Intel® FPGA Hard IP RX client interface allows the application to read frame data from the RX MAC segmented when it is received. Packets may start on any 8-byte segment.

Table 41.  Signals of the Avalon® Streaming RX Client InterfaceAll interface signals are clocked by the RX clock.

Name

Width

Description

o_rx_mac_data[1023:0]

o_rx_mac_data[511:0]

o_rx_mac_data[255:0]

o_rx_mac_data[127:0]

o_rx_mac_data[63:0]

1024 bits (400GE)

512 bits (200GE)

256 bits (100GE)

128 bits (50GE/40GE)

64 bits (25GE/10GE)

Output data to the MAC when the rate is 10GE/25/40GE/50GE/100GE/200GE/400GE. Bit 0 is the LSB.

o_rx_mac_valid

1 bit

When asserted, indicates that RX data is valid on this cycle

When deasserted, ignore the signals value.

i_rx_mac_inframe[15:0]

i_rx_mac_inframe[7:0]

i_rx_mac_inframe[3:0]

i_rx_mac_inframe[1:0]

i_rx_mac_inframe[0]

16 bits (400GE)

8 bits (200GE)

4 bits (100GE)

2 bits (50GE/40GE)

1 bit (25GE/10GE)

Indicates the valid data in each EMIB. With the previous segment's inframe signal, indicates the SOP and EOP location.

Each segment is 64 bits.

o_rx_mac_eop_empty[47:0]

o_rx_mac_eop_empty[23:0]

o_rx_mac_eop_empty[11:0]

o_rx_mac_eop_empty[5:0]

o_rx_mac_eop_empty[2:0]

48 bits (400GE)

24 bits (200GE)

12 bits (100GE)

6 bits (50GE/40GE)

3 bits (25GE/10GE)

Indicates the number of empty bytes on the RX data signal where EOC occurs, starting from the most significant byte (MSB).

o_rx_mac_fcs_error[15:0]

o_rx_mac_fcs_error[7:0]

o_rx_mac_fcs_error[3:0]

o_rx_mac_fcs_error[1:0]

o_rx_mac_fcs_error[0]

16 bits (400GE)

8 bits (200GE)

4 bits (100GE)

2 bits (50GE/40GE)

1 bit (25GE/10GE)

 Indicates that the currently ending frame has an error.

Valid only on EOP segments. A valid high on this signal indicates that the frame that is ending either had an FCS error, was malformed, was undersized, or was oversized and truncated because the MTU enforcement feature of the RX MAC was enabled.

o_rx_mac_error[31:0]

o_rx_mac_error[15:0]

o_rx_mac_error[7:0]

o_rx_mac_error[3:0]

o_rx_mac_error[1:0]

32 bits (400GE)

16 bits (200GE)

8 bits (100GE)

4 bits (50GE/40GE)

1 bit (25GE/10GE)

 Indicates that the currently ending frame has a decoding error.

The [1:0] bits for each segment accept values 0, 1, 2, and 3, and report different types of errors:

  • 2'd0: If FCS error is deasserted, the packet contains no error.
  • 2'd1: Malformed packet error. The IP core identifies a malformed packet when it receives a control character that is not a terminate character.
  • 2'd2: Undersized (frame shorter than 64b) or oversized (frame larger than the programmed maximum frame rate) frame.
  • 2'd3: Payload length error. The payload received in the frame is shorter than the length field value, and the value in the length field is less than or equal 1500 bytes. If the frame is oversized or undersized, the case is not reported here. If the frame is malformed, the case is not reported here.

o_rx_mac_status_data[47:0]

o_rx_mac_status_data[23:0]

o_rx_mac_status_data[11:0]

o_rx_mac_status_data[5:0]

o_rx_mac_status_data[2:0]

48 bits (400GE)

24 bits (200GE)

12 bits (100GE)

6 bits (50GE/40GE)

3 bits (25GE/10GE)

Specifies information about the received frame. If multiple status occur, the status is reported in 5, 4, 7, 6, 1, 2, 3, 0 priority order.

The individual bits report different information:

  • 3'd7: When asserted, indicates a FC (Length/Type is 0x8808) frame
  • 3'd6: When asserted, indicates illegal length frame
  • 3'd5: When asserted, indicates a SVLAN frame and a stacked VLAN frame
  • 3'd4: When asserted, indicates a SFC frame or PFC frame
  • 3'd3: When asserted, indicates a PTP (Length/Type is 0x88F7) frame
  • 3'd2: When asserted, indicates a BCAST frame and a MCAST frame
  • 3'd1: When asserted, indicates an Ethernet type frame that is not FC frame
  • 3'd0: When asserted, indicates a valid length frame
Figure 36. Receiving Data Using the RX MAC Client Interface

The figure above shows how to receive data using the RX MAC segmented client interface.

  • Packets may start on any 8-byte segment of i_tx_mac_data (Segmented). The i_tx_mac_inframe transition from 0 to 1 (between two consecutive segments) indicates a start of packet (SOP). The SOP begins at a segment where o_rx_mac_frame is set to 1.
  • For multisegmented interfaces, a new packet may start and the previous packet end are within the same cycle.
  • When the packet ends, o_rx_mac_eop_empty is set to the number of unused bytes in o_rx_mac_data.
    • The o_rx_mac_eop_empty transition from 1 to 0 (between two consecutive segments) indicates the end of packet (EOP). The EOP ends in the segment where o_rx_mac_inframe is set to 0.
    • The minimum number of bytes on the last cycle is 1.
Note: The interface does not take direct backpressure.
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