F-Tile Ethernet Intel® FPGA Hard IP User Guide

ID 683023
Date 3/28/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Give Feedback

9.1.6. Registers

The auto-negotiation and link training registers are available per each Ethernet port the F-Tile Auto-Negotiation and Link Training for Ethernet Intel® FPGA IP controls.

Refer to the F-tile Auto-Negotiation and Link Training Register Map to access register map and registers description. The register map documents the registers using the byte address offset.