F-Tile Ethernet Intel® FPGA Hard IP User Guide

ID 683023
Date 3/28/2022
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7.3. RX MAC Avalon ST Aligned Client Interface

The F-Tile Ethernet Intel® FPGA Hard IP RX client interface in MAC+PCS variations employs the Avalon® streaming interface protocol. The Avalon® streaming interface protocol is a synchronous point-to-point, unidirectional interface that connects the producer of a data stream (source) to a consumer of data (sink). The key properties of this interface include:

  • Start of packet (SOP) and end of packet (EOP) signals delimit frame transfers.
  • The SOP must always be in the MSB, simplifying the interpretation and processing of data you receive on this interface.
  • A valid signal qualifies signals from source to sink.

The RX MAC acts as a source and the client acts as a sink in the receive direction.

Table 36.  Signals of the RX MAC Avalon ST Client InterfaceAll interface signals are clocked by the RX clock (i_clk_rx). The signal names are standard Avalon® streaming interface signals.

Name

Width

Description

o_rx_data[511:0]

o_rx_data[127:0]

o_rx_data[63:0]

512 bits (100GE)

128 bits (50GE/40GE)

64 bits (25GE/10GE)

Output data to the MAC when the rate is 10GE/25/40GE/50GE/100GE. Bits 0 is the LSB.

o_rx_valid

1 bit

When asserted, indicates that RX data is valid. Only valid between the SOP and EOP signals.

This signal might be deasserted between the assertion of the SOP and EOP signals.

o_rx_empty[5:0]

o_rx_empty[3:0]

o_rx_empty[2:0]

6 bits (100GE)

4 bits (50GE/40GE)

3 bits (10GE/25GE)

Indicates the number of empty bytes on the RX data signal when EOP signal is asserted, starting from the least significant byte (LSB).

o_rx_startofpacket

1 bit

When asserted, indicates that the RX data signal holds the first clock cycle of data in a packet (start of packet). The IP core asserts this signal for only a single clock cycle for each packet.

When the SOP signal is asserted, the MSB of the RX data signal drives the start of packet.

o_rx_endofpacket

1 bit

When asserted, indicates that the RX data signal holds the final clock cycle of data in a packet (end of packet). The IP core asserts this signal for only a single clock cycle for each packet.

In the case of an undersized frame or in the case of a frame that is exactly 64 bytes long, the SOP and EOP signals might be asserted in the same clock cycle.

o_rx_error[5:0]

6 bits Reports certain types of errors in the Ethernet frame whose contents are currently being transmitted on the client interface. This signal is valid in EOP cycles only.

The individual bits report different types of errors:

  • Bit [0]: Malformed packet error. If this bit has the value of 1, the packet is malformed. The IP core identifies a malformed packet when it receives a control character that is not a terminate character.
  • Bit [1]: CRC error. If this bit has the value of 1, the IP core detected a CRC error, error character in the frame, malformed, undersized, or truncated packets..
  • Bit [2]: undersized or oversized frame.

    The IP core does not recognize an incoming frame of size eight bytes or less as a frame, and those cases are not reported here. If the preamble-passthrough and CRC forwarding settings cause the RX MAC to strip out bytes such that only eight bytes or less remain in the frame, the IP core also does not recognize the frame, and those cases are not reported here. If the frame is malformed, the case is not reported here.

  • Bit [3]: Reserved.
  • Bit [4]: payload length error. If this bit has the value of 1, the payload received in the frame is shorter than the length field value, and the value in the length field is less than or equal 1500 bytes. If the frame is oversized or undersized, the case is not reported here. If the frame is malformed, the case is not reported here.
  • Bit [5]: Reserved.

o_rxstatus_valid

1 bit When asserted, indicates that o_rxstatus_data is driving valid data.

o_rxstatus_data[39:0]

40 bits

Specifies information about the received frame. The following fields are defined:

  • Bits [39:38]: Reserved.
  • Bit [37]: When asserted, indicates a BCAST/MCAST frame
  • Bit [36]: Reserved
  • Bit [35]: When asserted, indicates a PAUSE frame
  • Bit [34]: When asserted, indicates a Control (Type is 0x8808) frame
  • Bit[33]: When asserted, indicates a VLAN frame and a stacked VLAN frame
  • Bits[32:0]: Reserved

o_rx_preamble[63:0]

64 bits

Reads the preamble value of an RX frame. This signal is valid when the o_rx_valid and the o_rx_startofpacket signals are asserted.

This signal is available only available when you turn on Preamble Passthrough in the parameter editor for 40GE/50GE channels.
Note: For preamble passthrough with other rates, use the first eight bytes of the o_rx_data signal.
Figure 32. Receiving Data Using the RX MAC Avalon ST Client Interface

The figure above shows how to receive data using the RX MAC Avalon ST client interface. The interface complies with the Avalon® streaming interface specification.

  • Packets always start on the MSB of o_rx_data (SOP aligned).
  • When the frame ends, o_rx_empty is set to the number of unused bytes in o_rx_data, starting from the right (byte 0).
    • In this example, o_rx_data on the last cycle of the packet has 5 empty bytes.
    • The minimum number of bytes on the last cycle is 1.
  • The framing and data ports are only valid when o_rx_data is high.
Note: The interface does not take direct backpressure.