IEEE 1588 V2 Test: Intel FPGA Programmable Acceleration Card N3000

ID 683017
Date 5/30/2020

3. lperf3 Traffic Test

This section describes the iperf3 traffic benchmarking test to further evaluate the PTP performance of the Intel® FPGA PAC N3000. The iperf3 tool has been utilized to emulate active traffic conditions. The network topology of the iperf3 traffic benchmarks, shown in the figure below, involves connection of two servers, each using a DUT card ( Intel® FPGA PAC N3000 and XXV710), to Cisco Nexus 93180YC-FX switch. The Cisco switch acts as a Boundary Clock (T-BC) between the two DUT PTP slaves and the Calnex Paragon-NEO Grandmaster.
Figure 8. Network Topology for Intel® FPGA PAC N3000 lperf3 Traffic Test
The PTP4l output on each of the DUT hosts provides data measurements of the PTP performance for each slave device in the setup ( Intel® FPGA PAC N3000 and XXV710). For iperf3 traffic test, the following conditions and configurations apply to all graphs and performance analysis:
  • 17 Gbps aggregated bandwidth of traffic (both TCP and UDP), either egress or ingress or bidirectional to Intel® FPGA PAC N3000.
  • IPv4 encapsulation of PTP packets, due to configuration limitation on Cisco Nexus 93180YC-FX switch.
  • PTP message exchange rate limited to 8 packets/second, due to configuration limitation on Cisco Nexus 93180YC-FX switch.