IEEE 1588 V2 Test: Intel FPGA Programmable Acceleration Card N3000

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ID 683017
Date 5/30/2020
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. IXIA Traffic Test 3. lperf3 Traffic Test 4. Conclusion 5. Document Revision History for IEEE 1588 V2 Test
1. Introduction x
1.1. Background 1.2. Objective 1.3. Features and Limitations 1.4. Tools and Driver Versions
2. IXIA Traffic Test x
2.1. IXIA Traffic Test Result
3. lperf3 Traffic Test x
3.1. lperf3 Traffic Test Result
1. Introduction
2. IXIA Traffic Test
3. lperf3 Traffic Test
4. Conclusion
5. Document Revision History for IEEE 1588 V2 Test

1.1. Background

The Intel FPGA Programmable Acceleration Card N3000 in a virtualized radio access network (vRAN) requires support for the IEEE1588v2 as a Precision Time Protocol (PTP) Telecom Slave Clocks (T-TSC) to schedule software tasks appropriately. The Intel Ethernet Controller XL710 in Intel® FPGA PAC N3000 provides the IEEE1588v2 support. However, the FPGA data path introduces jitter that affects the PTP performance. Adding a transparent clock (T-TC) circuit enables the Intel® FPGA PAC N3000 to compensate for its FPGA internal latency and mitigates the effects of the jitter, which allows the T-TSC to approximate the Grandmaster’s Time of Day (ToD) efficiently.

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