Visible to Intel only — GUID: GUID-D91A8D22-7517-45A1-A40B-F4EDFB209F23
Visible to Intel only — GUID: GUID-D91A8D22-7517-45A1-A40B-F4EDFB209F23
IP Component Reset Behavior
For your IP component, the reset assertion can be asynchronous but the reset deassertion must be synchronous.
The reset assertion and deassertion behavior can be generated from an asynchronous reset input by using reset synchronization. Add reset synchronization to your component with Platform Designer when you integrate your IP into a system.
For information about integrating your IP into a system, refer to Integrating Your IP Into a System.
For an example of adding reset synchronization, refer to the Platform Designer Sample example design.
Synchronizers are implemented to minimize synchronization failures due to metastability in asynchronous signal transfers. For more information about metastability, refer to “Managing Metastability with the Intel Quartus Prime Software” in Intel Quartus Prime Pro Edition User Guide: Design Recommendations.
When the reset is asserted, the component holds its busy signal high and its done signal low. After the reset is deasserted, the component holds its busy signal high until the component is ready to accept the next invocation. All component interfaces (agents, hosts, and streams) are ready only after the component busy signal is low.