Intel® oneAPI Programming Guide

Download PDF
ID 771723
Date 7/14/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Visible to Intel only — GUID: GUID-1B9D5C49-0D4E-46AC-A283-F97F034BFBF1

View Details

Document Table of Contents
Document Table of Contents x
Intel® oneAPI Programming Guide
Intel® oneAPI Programming Guide x
Introduction to oneAPI Programming oneAPI Programming Model oneAPI Development Environment Setup Compile and Run oneAPI Programs API-based Programming Software Development Process Glossary Notices and Disclaimers
Introduction to oneAPI Programming x
Intel oneAPI Programming Overview oneAPI Toolkit Distribution Related Documentation
oneAPI Programming Model x
Data Parallelism in C++ using SYCL* C/C++ or Fortran with OpenMP* Offload Programming Model Device Selection SYCL* Thread and Memory Hierarchy
oneAPI Development Environment Setup x
Use the setvars Script with Windows* Use the setvars Script with Linux* or MacOS* Use Modulefiles with Linux* Use CMake with oneAPI Applications
Use the setvars Script with Windows* x
Use a Config file for setvars.bat on Windows Automate the setvars.bat Script with Microsoft Visual Studio*
Use the setvars Script with Linux* or MacOS* x
Use a Config file for setvars.sh on Linux or macOS Automate the setvars.sh Script with Eclipse*
Compile and Run oneAPI Programs x
Single Source Compilation Invoke the Compiler Standard Intel oneAPI DPC++/C++ Compiler Options Example Compilation Compilation Flow Overview CPU Flow GPU Flow FPGA Flow
CPU Flow x
Traditional CPU Flow CPU Offload Flow
CPU Offload Flow x
Example CPU Commands Ahead-of-Time Compilation for CPU Architectures Control Binary Execution on Multiple CPU Cores
GPU Flow x
GPU Offload Flow Example GPU Commands Ahead-of-Time Compilation for GPU
FPGA Flow x
Why is FPGA Compilation Different? Types of SYCL* FPGA Compilation FPGA Compilation Flags Emulate and Debug Your Design Evaluate Your Kernel Through Simulation Device Selectors for FPGA FPGA IP Authoring Flow Fast Recompile for FPGA Generate Multiple FPGA Images (Linux only) FPGA BSPs and Boards Targeting Multiple Homogeneous FPGA Devices Targeting Multiple Platforms FPGA-CPU Interaction FPGA Performance Optimization Use of RTL Libraries for FPGA Use SYCL Shared Library With Third-Party Applications FPGA Workflows in IDEs
Emulate and Debug Your Design x
Emulator Environment Variables Emulate Pipe Depth Emulate Applications with a Pipe That Reads or Writes to an I/O Pipe Compile and Emulate Your Design Limitations of the Emulator Troubleshooting Discrepancies in Hardware and Emulator Results Emulator Known Issues
Evaluate Your Kernel Through Simulation x
Simulation Prerequisites Installing the Questa*-Intel FPGA Edition Software Set Up the Simulation Environment Compile a Kernel for Simulation Simulate Your Kernel Viewing Simulation Waveforms Troubleshoot Simulator Issues
FPGA IP Authoring Flow x
Code IP Components in SYCL* Emulate and Debug Your IP Component Evaluate Your IP Component Through Simulation FPGA IP Component Performance Optimization Synthesizing Your Component IP with Intel® Quartus® Prime Software Integrating Your IP Into a System Encrypt IP Components for Distribution
Code IP Components in SYCL* x
Customize RTL Interfaces Suggested Coding Styles Memory-Mapped Host Interfaces Host Pipes Agent IP Component Kernels Streaming IP Component Kernels Kernel Argument Interfaces Pipelined Kernels Stable Arguments IP Component Reset Behavior The printf Command
Memory-Mapped Host Interfaces x
Memory-Mapped Host Interfaces Using Unified Shared Memory Memory-Mapped Interface Unified-Shared-Memory Virtual Address Space Memory-Mapped Host Interfaces Using Accessors
Evaluate Your IP Component Through Simulation x
Debug During Verification
Integrating Your IP Into a System x
Adding IP into an Intel® Quartus® Prime Project Adding IP into a Platform Designer System
FPGA BSPs and Boards x
FPGA Board Initialization Obtain FPGA Hardware Image Information
Use of RTL Libraries for FPGA x
Object Manifest File Syntax of an RTL Library Restrictions and Limitations in RTL Support Intel® Stratix® 10 and Intel Agilex® 7 Design-Specific Reset Requirements for Stall-Free and Stallable RTL Libraries
API-based Programming x
Intel oneAPI DPC++ Library (oneDPL) Intel oneAPI Math Kernel Library (oneMKL) Intel oneAPI Threading Building Blocks (oneTBB) Intel oneAPI Data Analytics Library (oneDAL) Intel oneAPI Collective Communications Library (oneCCL) Intel oneAPI Deep Neural Network Library (oneDNN) Intel oneAPI Video Processing Library (oneVPL) Other Libraries
Intel oneAPI DPC++ Library (oneDPL) x
oneDPL Library Usage oneDPL Code Sample
Intel oneAPI Math Kernel Library (oneMKL) x
oneMKL Usage oneMKL Code Sample
Intel oneAPI Threading Building Blocks (oneTBB) x
oneTBB Usage oneTBB Code Sample
Intel oneAPI Data Analytics Library (oneDAL) x
oneDAL Usage oneDAL Code Sample
Intel oneAPI Collective Communications Library (oneCCL) x
oneCCL Usage oneCCL Code Sample
Intel oneAPI Deep Neural Network Library (oneDNN) x
oneDNN Usage oneDNN Code Sample
Intel oneAPI Video Processing Library (oneVPL) x
oneVPL Usage oneVPL Code Sample
Software Development Process x
Migrating Code to SYCL* and DPC++ Composability Debugging the DPC++ and OpenMP* Offload Process Performance Tuning Cycle oneAPI Library Compatibility SYCL* Extensions
Migrating Code to SYCL* and DPC++ x
Migrating from C++ to SYCL* Migrating from CUDA* to SYCL* for the DPC++ Compiler Migrating from OpenCL Code to SYCL* Migrating Between CPU, GPU, and FPGA
Composability x
C/C++ OpenMP* and SYCL* Composability OpenCL™ Code Interoperability
Debugging the DPC++ and OpenMP* Offload Process x
oneAPI Debug Tools for SYCL* and OpenMP* Development Trace the Offload Process Debug the Offload Process Optimize Offload Performance
Debug the Offload Process x
Using the SYCL* Exception Handler
Performance Tuning Cycle x
Establish Baseline Identify Kernels to Offload Offload Kernels Optimize Your SYCL* Applications Recompile, Run, Profile, and Repeat
Intel® oneAPI Programming Guide

Adding IP into a Platform Designer System

Level Two Title