Developer Guide

FPGA Optimization Guide for Intel® oneAPI Toolkits

ID 767853
Date 7/13/2023
Public

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Minimum Latency Flow

The minimum latency flow attempts to minimize your kernel latency at the cost of decreased fMAX. Use this flow to optimize latency-sensitive designs.

To compile your design with the minimum latency flow, pass the -Xsoptimize=latency flag to the icpx command, as shown in the following example:

icpx -fsycl -fintelfpga -Xshardware -Xsoptimize=latency <source_file>.cpp

The minimum latency flow applies the following compiler controls:

  • Disable hyper-optimized handshaking on Intel® Stratix® 10 and Intel Agilex® 7 devices.
  • Use zero-latency stall-free clusters exit FIFO.
  • Disable loop speculation.
  • Sets reinvocation delay on all loops to 1 thereby allowing new loop invocations to begin immediately after a previous loop invocation has completed.

The following table shows how you can manually override these underlying controls:

Description User Control
Hyper-optimized handshaking -Xshyper-optimized-handshaking=<auto|off|on>
Exit FIFO latency of stall-free clusters -Xssfc-exit-fifo-type=<default|zero-latency|low-latency>
Loop speculation [[intel::speculated_iterations(N)]]

[[intel::max_reinvocation_delay(N)]]

Loop reinvocation delay [[intel::max_reinvocation_delay(N)]]
NOTE:

These manual controls are beneficial in overriding one or more of the underlying controls without affecting other underlying controls implied by the -Xsoptimize=latency compiler flag.