Developer Guide

FPGA Optimization Guide for Intel® oneAPI Toolkits

ID 767853
Date 7/13/2023
Public

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Document Table of Contents

Document Revision History for the FPGA Optimization Guide for Intel® oneAPI Toolkits

Date Release Version Changes
July 2023 2023.2
  • Revised the note about SYCL streams support and mentioned about using sycl::ext::oneapi::experimental::printf for debugging kernels.
  • Updated all occurrences of -Xsno-interleaving=<global_memory_type> to -Xsno-interleaving=<global_memory_name>.
  • Revised the information in the following topics:
    • Optimization Targets
    • Minimum Latency Flow
    • Loop Analysis
    • Quartus (Static) Summary
    • Pipes
    • Simple Host-Device Streaming
    • Buffered Host-Device Streamting
  • Added the following new topics:
    • Generate Register Map Wrapper (-Xsregister-map-wrapper-type)
    • Maximum Throughput Without Area Optimization Heuristics Flow
    • Create a 2xclock Interface (-Xsuse-2xclock)
    • Host Pipes
    • Host Pipe Declaration
    • Host Pipe API
    • Host Pipes RTL Interfaces
March 2023 2023.1
  • Added max_reinvocation_delay loop attribute.
  • Updated the limitations of AC data types in Advantages and Limitations of Arbitrary Precision Data Types.
  • Added another option to the -Xshyper-optimized-handshaking compiler flag in Modify the Handshaking Protocol Between Clusters (-Xshyper-optimized-handshaking).
  • Updated the values of supported data types and math operations in Control Hardware Implementation of the Supported Data Types and Math Operations.
  • Rebranded Intel® Agilex™ as Intel Agilex® 7.
  • Added device_globals extension.
  • Added Minimum Latency Flow.
  • Added Optimization Levels.
  • Revised the information in Perform Kernel Computations Using Local or Private Memory.
  • Reorganized all extensions under FPGA Extensions.
  • Added examples of declaring ac_complex variables in Declare the ac_complex Data Type.
December 2022 2023.0
  • Revised all references to #include <CL/...> as #include <sycl/...>.
  • Revised all references to using namespace cl::sycl; as using namespace sycl;.
  • Revised all references to dpcpp compiler driver to icpx -fsycl.
  • Added a note about avoiding adding the result of the convert_to function to another ap_float variable in Conversion Rules for ap_float.
  • Added a note about constant propagation optimization technique in Operations with Explicit Precision Controls.
  • Added additional about values supported by N for the [[intel::num_simd_work_items(N)]] attribute in Specify Number of SIMD Work-Items.
  • Revised Latency Controls topic to include a section on using latency controls with stall-free loop.
  • Added information about ihc::FPsingle and ihc::FPdouble to Declare the ap_float Data Type and Additional Data Types Provided by the ap_float.hpp Header File.
  • Added new sections on explicit conversion functions in Declare the ac_fixed Data Type and Declare the ac_int Data Type topics.
  • Removed deprecation notice for hls_float data type renamed to ap_float.
  • Added additional information about using the Intel® oneAPI FPGA Reports tool in Review the Optimization Report (report.html).
September 2022 2022.3
  • Added a note about setting the safelen parameter with 0 or 1 in ivdep Attribute.
  • Added a note about applying the ivdep attribute to an array in ivdep Attribute.
  • Minor update to example code in max_interleaving Attribute.
  • Updated all images and made moderate updates in all topics in the Analyze the FPGA Early Image section.
  • Made minor updates in Pipes topic.
  • Updated Latency Controls (Beta) topic completely.
  • Added a note about using the buffer_location<index> on BSPs with heterogeneous memory support in combination with read-only cache in Partitioning Buffers Across Different Memory Types (Heterogeneous Memory).
  • Revised the guidance in Timing Failures.
  • Made minor revisions in Zero-Copy Memory Access and Prepinning Memory topics.
  • Added the following new topics:
    • System of Tasks (task_sequence) Extension
    • Task Functions
    • task_sequence Use Cases
April 2022 2022.2
  • Changed the document title Intel® oneAPI DPC++ FPGA Optimization Guide to FPGA Optimization Guide for Intel® oneAPI Toolkits.
  • Replaced all general references to DPC++ with SYCL.
  • Added new loop functions to the existing list in FPGA Loop Directives.
  • Added a new limitation and removed some existing limitations in Advantages and Limitations of Arbitrary Precision Data Types.
  • Replaced all references to https://hlslibs.org/ with a reference to the documentation at https://github.com/hlslibs/ac_types/blob/v3.7/pdfdocs/ac_datatypes_ref.pdf.
  • Made a minor update to the description in The pipe Class and its Use.
  • Modified all occurrences of [[cl::reqd_work_group_size(Z, Y, X)]] to [[sycl::reqd_work_group_size(Z, Y, X)]]. [[cl::reqd_work_group_size(Z, Y, X)]] is now deprecated.
  • Added the following new topics:
    • Control Hardware Implementation of the Supported Data Types and Math Functions (-Xsdsp-mode=<option>)
    • Latency Controls