Developer Reference

Migrating OpenCL™ FPGA Designs to SYCL*

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ID 767849
Date 12/16/2022
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Document Table of Contents
Document Table of Contents x
Migrating OpenCL™ FPGA Designs to SYCL*
Migrating OpenCL™ FPGA Designs to SYCL* x
Overview FPGA Design Flow Modify Your Design Flags, Attributes, Directives, and Extensions Histogram Design Example Walkthrough Additional Information Document Revision History for Migrating OpenCL FPGA Designs to SYCL* Notices and Disclaimers
Overview x
Prerequisites
Modify Your Design x
Basic Modifications Advanced Modifications
Basic Modifications x
Host Code Modification Device Code Modification
Advanced Modifications x
Host Code Modification Device Code Modification
Device Code Modification x
C++ Features in Device Code
Flags, Attributes, Directives, and Extensions x
General Information Flags FPGA Board-Specific Flags Compiler Flags Optimization Flags Memory Attributes Loop Directives Floating Point Optimizations Kernel Attributes Intra-kernel Registered Assignment Function Channels/Pipes APIs LSU Attributes
Histogram Design Example Walkthrough x
OpenCL Sample Code SYCL Sample Code SYCL Sample Code With Explicit Data Movement
Migrating OpenCL™ FPGA Designs to SYCL*

Modify Your Design

The following topics describe how to modify your OpenCL program into a SYCL* program:

  • Basic Modifications: Describes the basic host and device code modifications necessary to migrate your design.
  • Advanced Modifications: Describes the advanced modification techniques using some best-known methods that can improve your design performance, making it easier for you to scale and target new architectures, and reduce the amount of SYCL code.
Parent topic: Migrating OpenCL™ FPGA Designs to SYCL*
Level Two Title