Developer Reference

Migrating OpenCL™ FPGA Designs to SYCL*

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ID 767849
Date 12/16/2022
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Document Table of Contents
Document Table of Contents x
Migrating OpenCL™ FPGA Designs to SYCL*
Migrating OpenCL™ FPGA Designs to SYCL* x
Overview FPGA Design Flow Modify Your Design Flags, Attributes, Directives, and Extensions Histogram Design Example Walkthrough Additional Information Document Revision History for Migrating OpenCL FPGA Designs to SYCL* Notices and Disclaimers
Overview x
Prerequisites
Modify Your Design x
Basic Modifications Advanced Modifications
Basic Modifications x
Host Code Modification Device Code Modification
Advanced Modifications x
Host Code Modification Device Code Modification
Device Code Modification x
C++ Features in Device Code
Flags, Attributes, Directives, and Extensions x
General Information Flags FPGA Board-Specific Flags Compiler Flags Optimization Flags Memory Attributes Loop Directives Floating Point Optimizations Kernel Attributes Intra-kernel Registered Assignment Function Channels/Pipes APIs LSU Attributes
Histogram Design Example Walkthrough x
OpenCL Sample Code SYCL Sample Code SYCL Sample Code With Explicit Data Movement
Migrating OpenCL™ FPGA Designs to SYCL*

Flags, Attributes, Directives, and Extensions

This section provides a list of features in OpenCL and their equivalents in SYCL*. It is a handy reference for SYCL syntax, but for additional information about the meaning and behavior of each feature, refer to the Intel FPGA SDK for OpenCL Pro Edition Programming Guide and the FPGA Optimization Guide for Intel oneAPI Toolkits.

In cases where the behavior of features is similar but not perfectly equivalent between OpenCL and SYCL, the differences and alternatives are highlighted. The following topics are covered in this section:

Parent topic: Migrating OpenCL™ FPGA Designs to SYCL*
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