Developer Reference

Migrating OpenCL™ FPGA Designs to SYCL*

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ID 767849
Date 12/16/2022
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Document Table of Contents
Document Table of Contents x
Migrating OpenCL™ FPGA Designs to SYCL*
Migrating OpenCL™ FPGA Designs to SYCL* x
Overview FPGA Design Flow Modify Your Design Flags, Attributes, Directives, and Extensions Histogram Design Example Walkthrough Additional Information Document Revision History for Migrating OpenCL FPGA Designs to SYCL* Notices and Disclaimers
Overview x
Prerequisites
Modify Your Design x
Basic Modifications Advanced Modifications
Basic Modifications x
Host Code Modification Device Code Modification
Advanced Modifications x
Host Code Modification Device Code Modification
Device Code Modification x
C++ Features in Device Code
Flags, Attributes, Directives, and Extensions x
General Information Flags FPGA Board-Specific Flags Compiler Flags Optimization Flags Memory Attributes Loop Directives Floating Point Optimizations Kernel Attributes Intra-kernel Registered Assignment Function Channels/Pipes APIs LSU Attributes
Histogram Design Example Walkthrough x
OpenCL Sample Code SYCL Sample Code SYCL Sample Code With Explicit Data Movement
Migrating OpenCL™ FPGA Designs to SYCL*

Loop Directives

The following table summarizes the loop directives supported by OpenCL and their equivalents in SYCL*:

OpenCL Syntax SYCL Syntax Description
#pragma disable_loop_pipelining [[intel::disable_loop_pipelining]] Disables pipelining of a loop.
#pragma ii <n> [[intel::initiation_interval(n)]] Attempts to set the II for the loop that follows the attribute declaration.

#pragma ivdep

#pragma ivdep safelen(N)

#pragma ivdep array(array_name)

#pragma ivdep array, safelen

#pragma ivdep safelen, array

[[intel::ivdep]]

[[intel::ivdep(safelen)]]

[[intel::ivdep(array)]]

[[intel::ivdep(array, safelen)]]

[[intel::ivdep(safelen, array)]]

Ignores memory dependencies carried by the loop that the attribute is applied to.

NOTE:

This attribute applies only to the loop it is applied to, and not to any of the future loops that might appear as a result of the [[intel::loop_coalesce(N)]] attribute.

CAUTION:

Applying the ivdep attribute incorrectly results in functionally incorrect hardware and potential functional differences between the hardware run and emulation. The ivdep attribute is ignored in emulation.

#pragma loop_coalesce <loop_nesting_level> [[intel::loop_coalesce(N)]] Coalesces nested loops into a single loop without affecting the loop functionality.
NOTE:

If you want to use the ivdep attribute to ignore loop-carried dependencies, apply it to the loop that causes dependencies and not to any of the future loops that might appear as a result of the [[intel::loop_coalesce(N)]] attribute.

#pragma max_concurrency(N) [[intel::max_concurrency(n)]] Limits the concurrency of a loop in your kernel.
#pragma max_interleaving N [[intel::max_interleaving(n)]] Maximizes the throughput and hardware resource occupancy of pipelined inner loops in a loop nest by issuing new inner loop iterations as frequently as possible (minimizing the loop initiation interval).
#pragma speculated_iterations k [[intel::speculated_iterations(N)] Specifies how many cycles the loop exit condition can take to compute.
#pragma unroll N #pragma unroll N Unrolls a loop. You can also use it to avoid unrolling a loop explicitly.
#pragma nofusion [[intel::nofusion]] Disables automatic loop fusion when compiling your design.
#pragma loop_fuse [depth(N)] [independent] sycl::ext::intel::fpga_loop_fuse<v>(f) Fuses loops within the function f and up to a depth of v >= 1.
sycl::ext::intel::fpga_loop_fuse_independent<v>(f) Fuses loops within the function f up to a depth v >= 1 while overriding fusion-safety checks.
Parent topic: Flags, Attributes, Directives, and Extensions
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