Developer Reference
Migrating OpenCL™ FPGA Designs to SYCL*
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Memory Attributes
The following table summarizes the syntax of memory attributes supported in OpenCL and SYCL*:
| OpenCL Syntax | SYCL Syntax | Description |
|---|---|---|
| __attribute__(bank_bits(b0, b1, ...,bn)) | [[intel::bank_bits(b0, b1,..., bn)]] | Specifies that the local memory addresses should use bits (b0,b1,...,bn) for bank selection, where, (b0,b1,...,bn) are indicated in terms of word-addressing and not byte-addressing. |
| __attribute__(bankwidth(N)) | [[intel::bankwidth(N)]] | Specifies that the memory system implementing the local variable must have banks that are N bytes wide, where N is a power-of-2 integer value greater than zero. |
| __attribute__(force_pow2_depth(N)) | [[intel::force_pow2_depth(N)]] | Specifies that the memory implementing the variable or array has a power-of-2 depth. This attribute is enabled if N is 1 and disabled if N is 0. |
| __attribute__(max_replicates(N)) | [[intel::max_replicates(N)]] | Specifies that the memory implementing the local variable or array has no more than the specified number of replicates to enable simultaneous reads from the datapath. |
| __attribute__(memory("impl_type")) | [[intel::fpga_memory("impl_type")] | Specifies that the compiler must implement the local variable in a memory system. The optional impl_type argument controls what type of FPGA resources are used to implement that memory system. |
| __attribute__(merge("label", "direction")) | [[intel::merge("key","direction")]] | Merges of two or more variables or arrays defined in the same scope in a width-wise or depth-wise manner. |
| __attribute__(numbanks(N)) | [[intel::numbanks(N)]] | Specifies that the memory system implementing the local variable must have N banks, where N is a power-of-2 integer value greater than zero. |
| __attribute__(private_copies(N)) | [[intel::private_copies(N)]] | Specifies that the memory has a defined number of copies to allow simultaneous iterations of a loop at any given time. |
| __attribute__(register) | [[intel::fpga_register]] | Specifies that the variable must be carried through the pipeline in registers. |
| __attribute__(simple_dual_port_memory) | [[intel::simple_dual_port]] | Specifies that the memory implementing the variable or array should have read-only and write-only ports rather than read or write ports. |
| __attribute__(singlepump) | [[intel::singlepump]] | Specifies that the memory system implementing the local variable must operate at the same clock frequency as the kernel accessing it. |
| __attribute__(doublepump) | [[intel::doublepump]] | Specifies that the memory system implementing the local variable must operate at twice the clock frequency of the kernel accessing it. |