Developer Reference

Migrating OpenCL™ FPGA Designs to SYCL*

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ID 767849
Date 12/16/2022
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Document Table of Contents
Document Table of Contents x
Migrating OpenCL™ FPGA Designs to SYCL*
Migrating OpenCL™ FPGA Designs to SYCL* x
Overview FPGA Design Flow Modify Your Design Flags, Attributes, Directives, and Extensions Histogram Design Example Walkthrough Additional Information Document Revision History for Migrating OpenCL FPGA Designs to SYCL* Notices and Disclaimers
Overview x
Prerequisites
Modify Your Design x
Basic Modifications Advanced Modifications
Basic Modifications x
Host Code Modification Device Code Modification
Advanced Modifications x
Host Code Modification Device Code Modification
Device Code Modification x
C++ Features in Device Code
Flags, Attributes, Directives, and Extensions x
General Information Flags FPGA Board-Specific Flags Compiler Flags Optimization Flags Memory Attributes Loop Directives Floating Point Optimizations Kernel Attributes Intra-kernel Registered Assignment Function Channels/Pipes APIs LSU Attributes
Histogram Design Example Walkthrough x
OpenCL Sample Code SYCL Sample Code SYCL Sample Code With Explicit Data Movement
Migrating OpenCL™ FPGA Designs to SYCL*

Document Revision History for Migrating OpenCL FPGA Designs to SYCL*

Document Revision History
Date Release Version Changes
December 2022 2023.0
  • Revised all references to #include <CL/...> as #include <sycl/...>.
  • Revised all references to using namespace cl::sycl; as using namespace sycl;.
  • Revised all references to dpcpp compiler driver to icpx -fsycl.
  • Changed the flag -Xsboard to -Xstarget.
September 2022 2022.3
  • Replaced references to Intel® FPGA Add-on for oneAPI Base Toolkit with relevant information.
April 2022 2022.2
  • Changed the document title Migrating OpenCL FPGA Designs to DPC++ to Migrating OpenCL FPGA Designs to SYCL*.
  • Replaced all general references to DPC++ with SYCL.
  • Added a link to Autorun Kernels tutorial in Kernel Attributes.
  • Added sycl::ext::intel::fpga_loop_fuse<v>(f) and sycl::ext::intel::fpga_loop_fuse_independent<v>(f) functions in Loop Directives.
November 2011 2021.4 Initial release.
Parent topic: Migrating OpenCL™ FPGA Designs to SYCL*
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