Intel® Processor Graphics: Microarchitecture and ISA
Organizers: Jason Ross, Subramaniam Maiyuran and Guei-Yuan Lueh (all from Intel)
Email: {jason.ross, subramaniam.maiyuran, guei-yuan.lueh}@intel.com
Duration: Half Day
Slides:
Abstract
Intel® Processor Graphics is a power-efficient, high performance graphics and media accelerator integrated on-die with the Intel CPU. It is the graphics processor in the majority of desktops and laptops. The integrated GPU shares the last-level cache with the CPU, which permits fine-grained, coherent data sharing at low latency and high bandwidth. On-die integration enables much lower power consumption than a discrete graphics card. Performance of the GPU approaches a teraflop. In this tutorial, we will give an in-depth presentation of the architecture and micro-architecture of the media and graphics accelerator and Intel Graphics Instruction Set Architecture (ISA). The tutorial has three parts. Part one will focus on the system architecture, part two will present micro architecture of Intel Processor Graphics, part three will present Intel Graphics ISA and some examples.
Biographies of Organizers
Jason Ross is Principal Engineer in the Visual and Parallel Computing Group at Intel, where he leads analytical performance and power work in VPG Architecture. Prior to his architecture role, he was a technical marketing engineer in Intel's Data Center Group. Jason holds B.S. degrees in Computer Engineering and Mathematics from Kansas State University, an MBA from California State University, Sacramento, and two patents related to circuit board design.
Subramaniam Maiyuran is a Senior Principal Engineer in the Visual and Parallel Computing Group at Intel. He is the chief architect of Intel Graphics Execution Unit.
Ken Lueh is a Senior Principal Engineer in the Visual and Parallel Computing Group at Intel. He is the chief architect of the Intel Graphics Compiler.