Intel® SoC FPGA Bare-metal Developer Center

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Linux Networking, storage, multitasking, interprocess communication, synchronization, and more. You do not have to be a Linux kernel expert to use Linux in your project. For example, you could write a Linux user space application and access the FPGA intellectual property (IP) registers directly, similar to how a bare-metal application would behave.
RTOS Multicore processing, multitasking, interprocess communication, and synchronization, depending on RTOS. Using a simple RTOS is easy. It is similar to using the C libraries of functions that are already implemented, instead of writing those functions yourself.
Bootloader Faster boot time, and access to the features already implemented in the bootloader, such as mass storage and networking Available bootloaders are:
  • U-Boot: open-source GPL license, available on all SoCs
  • MPL: open-source 3-clause BSD license, available on all SoCs
  • UEFI: open-source 3-clause BSD license, not available on Arria® V SoC and Cyclone® V SoC
  • Example Name

    Description

    Device

    Compiler

    HardwareLib-16550

    Uses UART and interrupt APIs to implement a console application.

    Cyclone V

    ARMCC
    GCC

    HardwareLib-ECCL2

    Sets up the MMU tables and shows the ECC capabilities of the L2 cache.

    Cyclone V

    ARMCC
    GCC

    HardwareLib-FPGA

    Configures FPGA HPS using direct memory access (DMA), opens the H2F bridges and talks to a GPIO soft IP component inside the FPGA fabric.

    Cyclone V

    ARMCC
    GCC

    HardwareLib-SPI

    Communicates with a SPI EEPROM on an external board.

    Cyclone V

    ARMCC
    GCC

    HardwareLib-Timer

    Sets up timers and interrupts.

    Cyclone V
    Arria V
    Intel Arria 10

    ARMCC
    GCC

    HelloWorld-Baremetal Prints "hello world" message using semihosting. Cyclone V
    Arria V
    Intel Arria 10
    ARMCC
    GCC

    Example

    Description

    Device (Project File)

    Device (Readme File)

    DMA

    Initializes DMA, performs memory to memory transfers and zero to memory transfers.

    Arria V
    Cyclone V
    Intel Arria 10

    Arria V
    Cyclone V
    Intel Arria 10

    ECC

    Sets up and enables ECC for for on-chip RAM, SD/MMC, quad serial peripheral interface (SPI), DMA and L2 cache. Injects single/double bit errors and sets up the interrupts for single/double bit error detections.

    Arria V
    Cyclone V
    Intel Arria 10

    Arria V
    Cyclone V
    Intel Arria 10

    GPIO

    Sets up general-purpose input/output (GPIO) as output ports to drive HPS LEDs, and to sets up GPIO as input ports for HPS push buttons.

    Arria V
    Cyclone V
    Intel Arria 10

    Arria V
    Cyclone V
    Intel Arria 10

    I2C

    Communicates over I2C with LCD screen, EEPROM memory as well as between two I2C modules.

    Arria V
    Cyclone V
    Intel Arria 10

    Arria V
    Cyclone V
    Intel Arria 10

    Quad SPI

    Performs reading and writing to the quad SPI using generic block I/O mode, indirect mode and DMA mode. Also sets up MMU and caches.

    Arria V
    Cyclone V

    Arria V
    Cyclone V

    SD/MMC

    Initializes SD/MMC card, reads and writes using block I/O functions.

    Arria V
    Cyclone V

    Arria V
    Cyclone V

    Timer

    Uses timers in free-running, one-shot and watchdog modes. Performs global timer measurements.

    Arria V
    Cyclone V
    Intel Arria 10

    Arria V
    Cyclone V
    Intel Arria 10

    Unhosted Uses UART for printf output instead of semihosting. Also demonstrates how to boot a bare-metal program from a SD card.

    Arria V

    Cyclone V

    Arria V

    Cyclone V

    SPI Communicates between two SPI modules connected through the FPGA fabric.

    Arria V

    Cyclone V

    Intel Arria 10

    Arria V

    Cyclone V

    Intel Arria 10

    HPS-to-FPGA Bridges Exercises the memory mapped interfaces of the hard processor system (HPS) exposed to the FPGA fabric. Performs memory tests by writing and reading the HPS memory using various ports of the HPS and measures the performance of the data movements. Example

    Arria 10

    Cyclone V

    Resource

    Type

    Developed Skills

    Software Design Flow for an ARM-based SoC

    Free 27 Minutes Online Course

    • Explain the software development tools provided in the SoC Embedded Development Suite (EDS)
    • Explain the boot flow of the HPSCreate the second stage bootloader software from hardware software handoff files
    • Use the SoC EDS and hardware libraries to create a bare-metal or OS specific application
    • Select an operating system to run on the ARM processor
    • Perform FPGA-adaptive SoC Debug

    SoC Bare-metal Programming and Hardware Libraries

    Free 28 Minutes Online Course

    • Use the tools in the SoC EDS to develop bare-metal programs
    • Utilize the features of the hardware libraries to develop low-level software
    • Understand the SoC EDS features available to debug a bare-metal application

    Developing Software for an ARM-based SoC

    8 hours Instructor-Led / Virtual Class Course

    • Explain the hardware-to-software file handoff
    • Explain the stages in the HPS boot sequence & the boot scenarios
    • Create the second-state bootloader
    • Write bare-metal applications using Intel FPGA’s Hardware Libraries
    • Get started with a variety of OSs for the ARM processor
    • Use DS-5 Development Studio to perform FPGA-adaptive software debug

    SoC EDS Section

    Description

    Introduction

    Overview and the hardware-software development flow.

    Installing

    How to install the Intel SoC FPGA EDS and the ARM DS-5 Intel SoC FPGA Edition.

    Licensing

    Licensing options for the Intel SoC FPGA EDS and how to install the license.

    Embedded Command Shell

    How to start the shell and use it to access the rest of the Intel SoC FPGA EDS tools.

    ARM DS-5 Intel SoC FPGA Edition

    Basic operations, such as starting the ARM DS-5 Intel SoC FPGA Edition, bare-metal project management, and debugging.

    Hardware Libraries

    Overview of HWLIBs and how to get to the Doxygen information included with the Intel SoC FPGA EDS installation.

    Bare-Metal compilers

    Overview of the two bare-metal compilers included with the Intel SoC FPGA EDS: ARMCC and GCC.

    Guide

    Description

    Getting Started with Board Setup

    Set up the Intel SoC development board.

    Getting Started with Running the Tools

    Run some of the tools provided with the Intel SoC FPGA EDS.

    Getting Started with Basic Bare-metal Development

    Import, compile, and debug the Hello World bare-metal application example provided.

    Resource

    Description

    SoC FPGA EDS Download

    Download SoC FPGA EDS.

    Intel FPGA Development Kits

    See all the the available FPGA Development Kits. Click on SoC Series Kits on the left navigation pane to see the boards supporting an SoC FPGA.

    SoC FPGA Design Examples

    Access various design examples. Click on SoC Design Examples on the left navigation pane to see the examples targeting an SoC FPGA.

    Intel FPGA Training Curricula

    Access the entire Intel FPGA training curricula. Select Software Development on the left navigation pane, then search for "SoC" for specific SoC FPGA related courses. Or select any other areas of interest.

    Intel FPGA Training Catalog

    Access the entire Intel FPGA training catalog. Search for "SoC" for specific SoC FPGA related courses. Or select any other courses of interest.

    Intel SoC FPGA EDS Overview

    See an overview of the Intel SoC FPGA EDS, including what is new in the latest release, release notes, and release history.

    SoC FPGA Ecosystem

    Get links to various SoC FPGA related resources, such as operating systems, development tools, IP cores, and boards.

    Intel FPGA Engineer to Engineer Videos

    Access more than 200 videos created by Intel FPGA engineers. Some videos are generic, while others are related to SoC FPGA products.

    Intel Community

    Collaborate with other Intel FPGA users through this community website. Check out the Embedded Design Suite (EDS) and SoC Discussion sections. Use the search engine to find relevant material. All are encouraged to update and contribute.