Bare-metal development uses a software runtime environment that does not use an operating system (OS) or a real-time operating system (RTOS). In a bare-metal configuration, the hard processing system (HPS) of SoC FPGAs can be used. Intel offers hardware libraries (HWLIBs) that consist of high-level application programming interfaces (APIs) and low-level macros that enable you to exercise most of the HPS peripherals.
You can access various resources to help you get started with bare-metal development on Intel® SoC FPGAs from the links below. If you are a first-time user, we recommend that you follow the resources linearly.
Bare metal represents the actual register interfaces and hardware features of the processor system.
Bare-metal development uses a software runtime environment that does not use an OS or an RTOS.
In bare-metal configurations, the HPS of SoC FPGAs can be used. Intel offers HWLIBs that consist of high-level APIs and low-level macros that enable you to exercise most of the HPS peripherals.
The advantages of using a bare-metal approach are:
Absolute control of hardware
Minimal size (both flash and memory footprint)
No dependency on other source codes or libraries
Easier to formally prove correctness and perform code coverage analysis
Other reasons for selecting bare-metal development are:
Need to perform board bring-up and focus on one peripheral at a time
Need to re-use existing legacy code that is already developed as bare-metal
Lack of experience with an OS or RTOS
To develop a bare-metal application for the HPS, you must be familiar with developing runtime capabilities to ensure that your application makes efficient use of the resources available in your CPU subsystem. Examples of what may be required are as follows:
In-depth knowledge of the hardware platform
Developing runtime capabilities to manage the process between the core and the cache subsystem if you want to fully utilize the CPU subsystem, as a typical bare-metal application uses only a single core
Developing capabilities to manage and schedule processes, handle inter-process communications, and synchronize events within your application
If your scheduled project does not allow for effort it may take to become familiar with the above points, then it is recommended that you consider using a commercial Linux or RTOS solution.
Networking, storage, multitasking, interprocess communication, synchronization, and more.
You do not have to be a Linux kernel expert to use Linux in your project. For example, you could write a Linux user space application and access the FPGA intellectual property (IP) registers directly, similar to how a bare-metal application would behave.
Multicore processing, multitasking, interprocess communication, and synchronization, depending on RTOS.
Using a simple RTOS is easy. It is similar to using the C libraries of functions that are already implemented, instead of writing those functions yourself.
Faster boot time, and access to the features already implemented in the bootloader, such as mass storage and networking
Available bootloaders are:
U-Boot: open-source GPL license, available on all SoCs
MPL: open-source 3-clause BSD license, available on all SoCs
UEFI: open-source 3-clause BSD license, not available on Arria® V SoC and Cyclone® V SoC
If the ARM DS-5 Intel SoC FPGA Edition is used for debugging and/or tracing bare-metal applications, you will need to obtain a license. The license is typically included with your Intel SoC FPGA Development Kit purchase. Refer to the SoC EDS User Guide's license setup instructions.
There are two different types of projects that can be managed by the ARM DS-5 Intel SoC FPGA Edition:
Makefile-based projects: the project is managed by manually editing the makefile, and the ARM DS-5 Intel SoC FPGA Edition just calls 'make all' and 'make clean' on that makefile to build and to clean your project, respectively.
Plugin-based projects: The ARM DS-5 Intel SoC FPGA Edition completely manages your project, including files to compile, compiler options, building, and cleaning.
The advantage of a makefile-based project is that it can invoke any other tools, not just the bare-metal compiler, thus offering more flexibility. The only advantage of using a plugin-based project is that the settings are easily accessible from the ARM DS-5 Intel SoC FPGA Edition graphical interface as opposed to editing the makefile with a text editor.
You can also create your own projects using the following alternatives:
Option 1: Manually create a makefile, then follow these instructions to enable the project in the ARM DS-5 Intel SoC FPGA Edition as a makefile-based project. Manually creating the makefile is beyond the scope of this guide, and requires you to familiarize yourself with all the build tools and their options. If a makefile is required, the recommended method is to use the provided script to create it.
Option 2: Manually create a plugin-based project from scratch, following these instructions. This consists of manually reproducing the procedure that the provided script follows in order to create the project. Note that the script offers more features, and is the recommended method to create your project. This option is documented for reference only.
Option 3: Start with an existing project and modify it to suit your needs. This can be done especially for short tests and experiments but this method is not recommended.
Sets up and enables ECC for for on-chip RAM, SD/MMC, quad serial peripheral interface (SPI), DMA and L2 cache. Injects single/double bit errors and sets up the interrupts for single/double bit error detections.
exercises the memory mapped interfaces of the hard processor system (HPS) exposed to the FPGA fabric. Performs memory tests by writing and reading the HPS memory using various ports of the HPS and measures the performance of the data movements.
Intel FPGA Community is a community website enabling collaboration between Intel FPGA users. Check out the "Embedded Design Suite (EDS)" and "SoC Discussion" sections. Use the search engine to find relevant material. You are also are encouraged to update and contribute.
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Access the entire Intel FPGA training curricula. Select Software Development on the left navigation pane, then search for "SoC" for specific SoC FPGA related courses. Or select any other areas of interest.
Obtain knowledge on Intel FPGAs, technologies, tools, and their usage from the community. This website is a dynamic medium for sharing articles and projects, and a platform for collateral and design examples. Use the search engine to find relevant material. All are encouraged to update and contribute.
Collaborate with other Intel FPGA users through this community website. Check out the Embedded Design Suite (EDS) and SoC Discussion sections. Use the search engine to find relevant material. All are encouraged to update and contribute.