The D/AVE 2D is an Altera® Qsys and VHDL register transfer level (RTL) intellectual property (IP) developed for sophisticated vector-based graphic applications. D/AVE fits perfectly into the requirements of embedded systems.
Feature highlights:
- High quality anti-aliasing
- Subpixel accurate rendering
- Resolutions up to 2,048 x 2,048
- Extended rendering primitives supported in hardware (lines, circles, circle rings, triangles, quadrangles, and wedges)
- 16 blending modes
- Patterns and gradients with alpha channel on all primitives
- Textures up to 2048 x 1024
- Bilinear filtering
- Render to texture
- Texture blending
- No cost hardware clipping
- Flexible input and output formats for frame buffer and textures
- Very small core size
- Easy core integration
- Fully re-entrant driver
The D/AVE 2D core is available in two different versions. A standard version named D/AVE 2D-TS and a light version named D/AVE 2D-TL. The major difference between the cores is that D/AVE 2D-TL does not support performance counting and is slower in terms of pixel processing. The D/AVE 2D-TS render pipeline produces one pixel per cycle, D/AVE 2D-TL needs four cycles for a pixel.
In the Altera Qsys environment, D/AVE uses the Avalon® bus interface, which is tested on the Cyclone® and Stratix® device families (including SoCs). An AMBA® AHB™/APB™ bus interface is also available.
Required Hardware and Software
Nios® II Embedded Evaluation Kit, Cyclone III Edition
Download This Design Example
This design ships with the Nios II Embedded Evaluation Kit, Cyclone III Edition. You can download the design example from the TES website.
Contact TES for support for this design example.
The use of this design is governed by, and subject to, the terms and conditions of the Altera Hardware Reference Design License Agreement.
TES D/AVE Demo
Figure 1 shows examples of vector graphics, subpixel processing, and the anti-aliasing functionality of the D/AVE graphics accelerator implemented in a Nios II processor-based system.
