VHDL: Node Synchronization Design Example for Viterbi Decoder

The node synchronization design shows how to resynchronize a system at the receiver where the encoded symbols may have undergone a phase shift during transmission over the channel. The decision to rotate the encoded symbols prior to feeding them into the Viterbi decoder is made based on the monitoring of the number of errors detected by the Viterbi decoder, denoted by the numerr signal.

Download the files used in this example:

The use of this design is governed by, and subject to, the terms and conditions of the Altera Hardware Reference Design License Agreement.

Files in the zip download include:

  • viterbi_node_sync.vhd - Top-level design file
  • ber_node_sync.vhd - Wrapper file for ber_threshold and rotate_node_sync blocks
  • viterbi_BER.vhd – Wrapper file for Viterbi decoder implemented using the Viterbi Compiler intellectual property (IP) block
  • ber_threshold.vhd – Monitors the bit error rate (BER) and determines if system is in or out of sync
  • rotate_node_sync.vhd – Rotates encoded symbols based on decision made from the ber_threshold block
  • viterbi_node_sync_testbench.vhd – Testbench for register transfer level (RTL) simulation
  • run_script.tcl - Tool command language (Tcl) script to set up project for running functional simulation using ModelSim®
Figure 1. Viterbi Decoder Node Synchronization Top-Level Block Diagram

Implementation

The design example consists of the Viterbi Compiler intellectual property (IP) core and the ber_node_sync block which performs the monitoring of the BER as well as the synchronization process. The Viterbi Compiler IP core has the following parameters:

Table 1. Viterbi Compiler Parameters for viterbi_BER block

Parameters

Value

Architecture

Parallel

BER

On

Node Sync

On

Constraint Length

7

Traceback

42

Softbits

4

Bmgwide

9

Code Sets

Mode

V

GA

91

GB

121

N

2

L

7

Test Data

Number of Bits per Block

2048

Signal to Noise Ratio (dB)

8.0

Number of Blocks

8

Puncturing Patterns

Pattern A

11

Pattern B

11

The ber_threshold block monitors the number of errors based on the numerr signal from the viterbi core. If the number of errors within the sampling window is above the specified threshold value, the out_sync signal is asserted to indicate the system is out of sync. This will also initiate the node synchronization search process carried out in the rotate_node_sync block. The encoded bits are rotated in a predetermined manner (see Table 2). As a result of being out of sync, the testbench used to generate the continuous stream of data also gets restarted. This is accomplished by ending the current frame by asserting the sink_eop, and restarting the new frame by asserting the sink_sop. The BER monitoring process is restarted when any of the following conditions occur:

i) System reset

ii) System is out of sync

iii) Restarting a new sampling window (reached the end of the monitoring length)

iv) Start of a new frame (indicated by sink_sop) by the testbench

The design example assumes the system has the encoded symbols mapped into a QPSK mapping scheme in the transmitter. Hence the receiver requires the synchronization mechanism to rotate the two symbols (R1, R2) in a four-phase rotation which requires sign swapping. The node_state_sync signal denotes the status of the rotation as indicate in Table 2. The phase rotation can be easily changed to accommodate different mapping schemes.

Table 2. Phase Rotation for Encoded Symbols

State of node_state_sync

Phase Rotation

00

R1, R2

01

R2, -R1

10

-R1, -R2

11

-R2, R1

Figure 2. Viterbi Decoder Node Synchronization Flow Chart

Signals Description

In addition to the signals specified for the Viterbi core, the design example has the following signals:

Table 3. Signal Description

Signal

Description

out_sync

Asserted if the number of errors detected in the sampling window (length of monitoring window is specified by BER_monitor_len ) is greater than BER_threshold_val

node_state_sync

Status of the rotaton (four phases based on QPSK)

rr_rotate

Rotated input symbols

Parameters Description

In addition to the parameters specified for the Viterbi core, the design example has the following parameters:

Table 4. Parameter Description

Parameter

Description

BER_threshold_val

If the number of errors detected in the sampling window (length of monitoring window is specified by BER_monitor_len ) is greater than BER_threshold_val, then the system is out of sync

BER_monitor _len

Number of bits/sample for monitoring

numerr_max

Bit width for the counter tracking the number of errors detected

monitor_len_max

Bit width for the counter tracking the number of bits in the sampling window

Related Links

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