The node synchronization design shows how to resynchronize a system at the receiver where the encoded symbols may have undergone a phase shift during transmission over the channel. The decision to rotate the encoded symbols prior to feeding them into the Viterbi decoder is made based on the monitoring of the number of errors detected by the Viterbi decoder, denoted by the numerr signal.
Download the files used in this example:
The use of this design is governed by, and subject to, the terms and conditions of the Altera Hardware Reference Design License Agreement.
Files in the zip download include:
- viterbi_node_sync.vhd - Top-level design file
- ber_node_sync.vhd - Wrapper file for ber_threshold and rotate_node_sync blocks
- viterbi_BER.vhd – Wrapper file for Viterbi decoder implemented using the Viterbi Compiler intellectual property (IP) block
- ber_threshold.vhd – Monitors the bit error rate (BER) and determines if system is in or out of sync
- rotate_node_sync.vhd – Rotates encoded symbols based on decision made from the ber_threshold block
- viterbi_node_sync_testbench.vhd – Testbench for register transfer level (RTL) simulation
- run_script.tcl - Tool command language (Tcl) script to set up project for running functional simulation using ModelSim®