This page consists of design examples for state machines in VHDL. A state machine is a sequential circuit that advances through a number of states. The examples provide the HDL codes to implement the following types of state machines:
4-State Mealy State Machine
The outputs of a Mealy state machine depend on both the inputs and the current state. When the inputs change, the outputs are updated without waiting for a clock edge.
4-State Moore State Machine
The outputs of a Moore state machine depend only on the present state. The outputs are written only when the state changes (on the clock edge).
Safe State Machine
This example uses the syn_encoding synthesis attribute value safe to specify that the software should insert extra logic to detect an illegal state and force the state machine's transition to the reset state.
User-Encoded State Machine
This example uses the syn_encoding synthesis attribute to apply specific binary encodings to the elements of an enumerated type.
Download the files used in this example:
- Download mealy_state_machine_vhd.zip
- Download moore_state_machine_vhd.zip
- Download safe_state_machine_vhd.zip
- Download user_encoded_machine_vhd.zip
- Download VHDL Template for State Machines README File
Each zip download includes the VHDL file for the state machine and its top level block diagram.