Achieving Unity Gain in Block-Floating-Point IFFT+FFT Pair

The FFT MegaCore® function supports block-floating-point (BFP) architecture, a trade-off between fixed-point and full floating-point architecture. The BFP FFT receives fixed-point input data and calculates the fixed-point output data with exponent input. Due to a lack of an exponent input port in FFT, when cascading IFFT with FFT, the scaling factor must be computed externally. This design example describes how to achieve unity gain in a BFP IFFT+FFT pair with scaling arithmetic with an Altera® FFT MegaCore function.

Download the files used in this example:

The use of this design is governed by, and subject to, the terms and conditions of the Hardware Reference Design License Agreement.

Files in the download include:

  • BFP_unitygain.v - Top-level design file implementing the cascaded IFFT+FFT system
  • tb_BFT_unitygain.v - Testbench for RTL functional simulation
  • BFP_unitygain.tcl - TCL script to automate ModelSim® simulation
  • unity_gain_tb.m - MATLAB script to compare the difference between BFP output with floating-point output
Figure 1. BFP IFFT+FFT Unity Gain Top-Level Block Diagram
Figure 2. FFT I/O Port Signals

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The use of this design example is governed by, and subject to the terms and conditions of the Intel® Design Example License Agreement.

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