Octera SPI-4.2-to-Xaui Bridge Reference Design

The use of this design is governed by, and subject to, the terms and conditions of the Intel Design Example License Agreement.


The Octera XAUI SPI-4.2 Bridge provides a customizable framework to act as a starting point for more complex FPGA-based packet processing solutions for bridging applications. The design framework offers a highly optimized bridge function from custom XAUI to single or multi-channel SPI-4.2 ports.

For more complex FPGA designs, Octera uses a range of tools suitable for developing packet coprocessing in an overall system, perhaps containing a network processor or customer ASIC. These include a traffic generator, a library of C++ models of common packet processing functions, bus functional models, a complete register transfer level (RTL) environment, and a hardware platform. This allows you to model the FPGA packet processing in your own environment and then to generate a model of the required FPGA. Octera supplies RTL source code of base modules or customizes the modules on the your behalf.


  • Supports 10 GbE, custom XAUI including Broadcom HiGig, HiGig+ protocols and will support emerging HiGig2 protocols
  • Supports user-defined headers
  • Programmable 1-18 PL4 channels
  • Offers common packet processing, header extraction/insertion, tag insertion/deletion, VLAN processing, packet reassembly and priority queuing, and scheduling
  • Customizable modular design
  • C++ environment allows modeling of FPGA design in overall system

Block Diagram

Figure 1 shows the block diagram of a fully populated Octera SPI-4.2-to-XAUI bridge transmit and receive path.

Figure 1. Octera SPI-4.2-to-Xaui Bridge Reference Design

Figure 1. Octera SPI-4.2-to-Xaui Bridge Reference Design

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  1. FC = Fibre Channel
  2. PL4 = POS-PHY Level 4
  3. CRC = Cyclic Redundancy Check
  4. PCS = Physical Coding Sublayer

Devices Targeted

Depending on the modules used, the design fits in:

  • EP2SGX30F780C5N devices for HiGig protocol (C4 for HiGig+) in a basic configuration
  • EP2SGX60F780C5N devices for HiGig protocol (C4 for HiGig+) for a more complex configuration

Demonstrated Intel Technology


  • Source code of the specified customer design
  • Test bench,including
    • Traffic generation
    • System modeling
    • Bus functional modules including XAUI, XGMII, PL4, and Avalon® host buses
    • Checkers
    • Script interface

Contact Information

For more information, please contact:

Octera Corporation
15470 Markar Road
Poway, CA 92064
Tel: (858) 375-4100
Email: info@octera.com
URL: www.octera.com

Reference Designs Disclaimer

These reference design illustrations remain the copyrighted property of Intel or its licensors and may be used within Intel Corporation devices only. They are being provided on an "as-is" basis and as an accommodation, and therefore all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Intel expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Intel.

Third-Party Trademark Notice

Broadcom®, HiGigTM, HiGig+TM, and HiGig 2TM are trademarks of Broadcom Corporation and/or its affiliates in the United States, certain other countries and/or the EU.